Papers by Author: Seung Boo Jung

Abstract: Light Emitting Diode (LED) has been already familiar that is used as lighting sources of general electronic devices and various displays. LED has many advantages such as long life, low power consumption and high reliability. In the future, as alternative to fluorescent lighting, it is sure that LED in lighting products is expected to receive much attention. However, the components related with advanced LED packages or modules have been issued on the heat from LED chip. And the LED chip is still being developed to the high power devices which are generating more heat. In this study, we investigated the variation of thermal resistance in LED modules embedded with thermal via. Through the analysis of thermal resistance with various test vehicles, we could obtain the concrete relationship between thermal resistance and structure of thermal via.

Abstract: The LED chips, packages and related materials have been already key issue on electronic applications and substitution of conventional lights. It is easily expected that the development trend of LED products is nearly the same as that of electronic products with higher performance, higher integration, lower energy and lower cost. And then we also prospect that the dissipated heat from LED chip is to be big problem for a reliability of products, as likely that electronic packages contain heat sink or heat spreader for controlling heat dissipation. In fact, the heat from an LED package with 1~3W LED chip shows a nearly 60~150°C, which affects thermal damage related to performance, joint failure, crack, etc. The thermal via was fabricated with 16 segments of via sizes ranged 0.2~1.2mm and via pitches ranged 0.5~3mm using 1~3W LED, respectively. The thermal resistivity was analyzed by the thermal transient tester with the variation of via sizes and pitches, which was also compared with the temperature difference of the top and bottom side of LED package. As a results, we convincingly proved the relationships between the design of thermal via and the heat dissipation of LED module, which were directly applicable to LED industry.

Abstract: The PET-ITO substrate has been usually applied to many flexible applications such as selectively conducting films, flexible printed circuit, display panels, interconnections, terminals, etc., where the PET-ITO substrate has a main role to enhance the performance in the components of touch screen panels, solar cell panels and so on. Today’s flexible technology is issued on forming fine pattern, pattern alignment and mass-productivity on PET-ITO substrates, which is strongly related to thermal shrinkage and expansion of the substrate[1~5]. We investigated in this study the thermo-mechanical behavior of PET-ITO substrate using a thermo-mechanical analyzer (TMA) in order to analyze thermal strain with varying temperature.

Abstract: Light emitting diode (LED) has been largely used in industry of consumer electronics such as cell-phones, PDAs, and computers. Since all light sources convert electric power into radiant energy and heat, LED also does the same with an increase of its power. Generally, it only converts 15~25% of electric power into visible light; the rest of the power, 75~85%, is converted into heat. This excess heat should be conducted away from the LED die to circuit boards or heat sinks since heat affects directly performance of the LED. The piled heat in LED products brings color shift and reduces light output very rapidly. Furthermore, the lifecycle of LED products shorten if the heat problem continues. In order to prevent LED products from these negative effects, effective thermal resistance paths need to be achieved so that LED products let the heat conduct from the LED to the outside such as printed circuit board. In this research, optimization studies on thermal-via is to be performed. The 1W and 3W LED assembled printed circuit board with 16 different via designs is set up to measure its temperature for 4 hours in a real time. It was obtained by this work that the optimized thermal via was very effective to dissipate the heat from the LED.

Abstract: In an optical module with high density and small size, it is important to maintain the operating temperature by adequate heat dissipation. The thermal simulation of an optical module for communication has been performed to reduce the operating temperature. To improve the behavior of heat dissipation, we have simulated heat path and heat resistance using commercial code, COMSOL. We have chosen simulation parameters, which include thickness, thermal conductivity, interface area and surface roughness of heat sink and submount as an element of heat resistance. To reduce heat resistance, it was desirable to use the material of higher thermal conductivity, single crystalline silver, and to control the surface roughness of the interfaces. We could lower the operating temperature of an optical module about 18 degrees by controlling the above parameters.

Abstract: The grain growth behavior and mechanical properties in the friction stir weld zone after post weld heat treatment (PWHT) have been investigated. As PWHT temperature increased, a normal grain growth of as-welded equaxied grains ceased and abnormally grown grains with elongated shape coarsened. Huge elongated grains changed into smaller equaxied grains at 500°C. In case of lower heat input condition, abnormal grain growth initiated faster due to smaller initial grain size. The weld zone with bigger initial grains had advantages to maintain the thermal stability at high temperature. The hardness near the weld zone was almost recovered to the 95% of the unaffected base metal at 500 °C and the weld zone under lower heat input condition resulted in the homogeneous recovery through the whole weld zone.

Abstract: Cube textured Ni substrate were fabricated for YBCO coated conductors from the initial specimens prepared by powder metallurgy (P/M) and casting and the effects of annealing temperature and reduction ratio on texture formation and microstructural evolutio were evaluated. The initial specimens were rolled by 98.6% and 99.2% reduction ratio and then annealed in the temperature range of 600°C to 1200°C. The microstructure and texture were evaluated by optical microscopy and X-ray pole-figure analysis. We observed that microstructure of the initial specimen varied with preparation methods.Texture analysis indicated that a strong cube texture formed for substrate made by P/M, and the degree of texture did not significantly vary with annealing temperature of 600°C~1100°C. On the other hand, the texture of substrate made by casting was more dependent on the annealing temperature and twin texture ({221}<221>) and several minor texture components started to form at 1000°C. In addition, the texture of substrate made by P/M was significantly dependent on the reduction ratio.

Abstract: The thermal fatigue properties of the solder joints with various underfills were evaluated by thermal shock test. Flip chip package with electroless nickel-immersion gold plated on Cu pad of FR-4 substrate and the Sn-37Pb solder ball was used. The thermal fatigue crack initiated at the edges of interface between solder and silicon die. The fatigue property of package with underfill, which has a higher glass transition temperature (Tg) and lower coefficient of thermal expansion (CTE) value was better than that of package with underfill having a lower Tg and higher CTE.

Abstract: The polystyrene spheres coated with a slurry, consisting of copper (I) oxide powder, water and PA (poly acrilamide), were reduced to form copper (Cu) hollow spheres at sintering temperatures ranging from 650 to 950 °C under a hydrogen atmosphere. The microstructural evolutions and mechanical properties of the Cu hollow spheres were investigated with the sintering temperature. The increase in the sintering temperature led to the increase in the density and grain size of the spheres. The amount of the residual copper oxide in the samples decreased with increasing sintering temperature. The electrical conductivity, hardness, and compression strength of the hollow spheres increased with increasing sintering temperature.

Abstract: Thermal fatigue properties of solder joints encapsulated with underfill were studied conducting thermal shock tests. Flip chip package with electroless nickel-immersion gold plated on FR-4 substrate and the Sn-3.0Ag-0.5Cu solder ball was used. The fatigue property of package with underfill was better than the package without it. The fatigue property of package with underfill which has a higher glass transition temperature (Tg) and lower coefficient of thermal expansion (CTE) was better than that of package with underfill with lower Tg and higher CTE.