Papers by Author: Shinsuke Harada

Abstract: MeV-SJ-MOSFET with short tapered SJ columns was developed by high-energy (MeV) Al ion implantation and was evaluated for the reverse recovery characteristics and the body diode reliability compared to those of Multiepi-SJ. MeV-SJ alleviated the increase in on-resistance at elevated temperatures regardless of short SJ columns and exhibited soft reverse recovery characteristics due to the short tapered SJ shape. MeV-SJ also suppressed the body diode degradation more than Multiepi-SJ. It was considered that the carrier lifetime of drift layer of MeV-SJ may be decreased by non-radiative defects.

Abstract: In this study, 4H-SiC bonded substrates (bonded-SiC) with an average resistivity of 2.4–31.5 mΩ·cm were prepared, and attention has been directed toward the relationship between the resistivity of bonded-SiC and the contact resistance at the backside where metal Ti/Ni was applied. A circular transmission line model (cTLM) was used to accurately measure the backside contact resistance. A linear correlation was found between and the resistivity of bonded-SiCs at room temperature (RT). This result indicates the existence of a threshold resistivity at which the specific contact resistance in the range of 2.2 × 10⁻⁶ to 1.5 × 10⁻⁵ Ω·cm² can be achieved without contact annealing; it also indicates that the temperature dependence of between 17.4 and 34.4 mΩ·cm is eliminated. This phenomenon can occur because is dominated by tunneling current above the nitrogen concentration at the threshold resistivity, which is driven by the high nitrogen concentration and sufficient carrier activation in the polycrystalline portion (polycrystalline layer) of bonded-SiCs. These are important properties resulting from a polycrystalline layer with a 3C structure in bonded-SiC.

Abstract: A unique hybrid structure of the 4H-SiC bonded substrate offers advantages not achievable with conventional 4H-SiC bulk substrates, such as a reduction in on-state resistance and the suppression of forward bias degradation in power devices. This study focuses on the contact resistance between the polycrystalline layer and the backside metal (Ni/Ti) of 4H-SiC bonded substrates, along with its temperature dependence. The results indicate that the bonded substrates exhibit low backside specific contact resistance (SCR) , even without annealing, and this resistance remains stable at elevated temperatures. Furthermore, power devices utilizing bonded substrates demonstrated reduced on-state resistance, as evaluated using Schottky barrier diodes (SBDs). Specifically, 4H-SiC bonded substrates without contact annealing lowered the forward voltage by 13.4% at room temperature (RT) compared to 4H-SiC bulk substrates with contact annealing. These findings suggest that 4H-SiC bonded substrates simplify the backside contact process compared to 4H-SiC bulk substrates, offering significant benefits in reducing on-state resistance in SiC power devices.

Abstract: In this study, we investigated the generation of trap centers through hydrogen implantation to understand its role in the suppression of forward bias degradation in 4H-silicon carbide (4H-SiC) bonded substrates. During the production of bonded substrates, hydrogen implantation is used for layer splitting. Transmission electron microscopy (TEM) observations revealed that the basal plane dislocation (BPD) in the bonded substrate did not extend into the Shockley-type stacking fault (SSF) and remained stable in the transferred layer below the epitaxial interface even under high forward current stress. Additionally, carrier lifetime, measured using microwave photoconductivity decay (μ-PCD), was considerably reduced by hydrogen implantation. Annealing at 1700°C reduced the implanted hydrogen to levels below the detection limit of secondary ion mass spectrometry (SIMS), yet the carrier lifetime remained short. Deep level transient spectroscopy (DLTS) revealed that, after annealing at 1700°C following hydrogen implantation, the concentration of the Z_1/2 center increased by more than two orders of magnitude compared to pre-implantation levels. Trap centers, including the Z_1/2 center, are believed to help prevent forward bias degradation in the bonded substrates by inhibiting the expansion of SSFs in the transferred layer.

Abstract: A novel substrate of 4H-SiC bonded substrate is expected to solve issues such as decreasing the on-resistance, which has attracted much attention. Therefore, several studies have been conducted on the use of bonded substrates. In this study, we fabricated a DMOSFET on a bonded substrate and compared its static and dynamic characteristics with those on a single-crystal substrate. Consequently, the on-resistance of the DMOSFET fabricated on a bonded substrate was lower than that on a single-crystal substrate owing to the low resistivity of the polycrystalline substrate. Also, reverse recovery loss of the DMOSFET fabricated on a bonded substrate was lower than that on single-crystal substrate at high temperature due to low carrier lifetime in a drift layer. Additionally, we observed that the DMOSFET fabricated on a bonded substrate did not generate bipolar degradation despite the application of a forward-current stress of over 1500 A cm^-2. According to these results, we expected that the carrier lifetime in both drift layer and transfer layer was decreased on a bonded substrate.

Abstract: In this study, the simultaneous realization of high-speed and high-temperature switching operations is demonstrated using a custom-made high-speed and high-temperature power module installed with a silicon carbide (SiC) CMOS gate driver, which can reduce gate loop inductance and operate at high temperatures. Approximate switching speeds of 70 and 60 V/ns are achieved during the turn-on and turn-off operations, respectively, at 300°C, 600 V DC bus voltage, and 20 A load current using the developed module. The switching speed remained above 50 V/ns in the temperature range from room temperature to 300°C. Numerical calculations based on the static properties of the SiC power MOSFET and CMOS gate driver can predict the actual switching properties over a wide temperature range when the developed module incorporating the fabricated SiC CMOS gate driver is used.

Abstract: Analysis of forward bias degradation reduction of 4H-Silicon Carbide (4H-SiC) PiN diodes on bonded substrates was performed. In the analysis, cathodoluminescence (CL), photoluminescence imaging (PL imaging), and transmission electron microscope (TEM) were used. Under high forward bias stress, the Shockley-type stacking fault (SSF) does not expand into the transferred layer of the bonded substrate, while in the monocrystalline substrate, the SSF expands below the epilayer/substrate interface. The basal plane dislocation (BPD) within the transferred layer does not expand to the SSF. The transferred layer has the effect of suppressing the expansion of SSFs. This effect can be caused by hydrogen implantation for wafer splitting to produce bonded SiC substrates.

Abstract: Single Event Gate Rupture (SEGR) is one of the catastrophic failures caused by heavy ions in power MOS devices. In this study, n-type SiC MOS capacitors representing the gate structure generally used in SiC power MOSFETs were used to conduct heavy ion irradiation tests to clarify the SEGR mechanism. The Linear Energy Transfer (LET) dependence of the critical electric field (E_cr) for these capacitors was evaluated with two different oxidation processes in accumulation to confirm whether the oxidation process affects SEGR tolerance. We found that the E_cr value and slopes of the LET dependence for SEGR between DRY samples and DRY + POA samples were approximately consistent. We also simulated SEGR and studied its mechanism. The simulation results suggested that SEGR for SiC MOS capacitors is caused by carriers in electron-hole pairs generated by a heavy ion instead of gate electric field fluctuation.

Abstract: Channel density design guidelines for SiC trench-gate MOSFETs with low switching loss, and high short-circuit and avalanche capabilities were proposed. The cell and grounding region pitches were used as parameters to control the channel density to investigate the parameter dependence of each transient property. The results suggest a clear difference in the dependence of switching loss reduction and short-circuit/avalanche capability increase on these parameters; however, the extents of dependence of specific on-resistance on the controlling parameters were comparable. The reduction in the grounding region pitch contributed to faster charging of the parasitic drain-source capacitance, which was effective in improving transient characteristics, such as dV/dt at turn-off, and saturation current at short-circuit. Furthermore, a reduction in this distance increased the area-flowing avalanche current and hence, an increase in the avalanche energy. The influence of the two design parameters in effectively improving the trade-off between each transient characteristic and the specific on-resistance was summarized.

Abstract: The advantage in reducing forward bias degradation of bipolar 4H-SiC devices using a 4H-SiC bonded substrate is demonstrated. To evaluate the differences in forward bias degradation between a 4H-SiC bonded substrate and a commercially available 4H-SiC bulk substrate, a forward current stress test and subsequent photoluminescence (PL) imaging of PiN diodes fabricated on both the substrates were performed. Unlike the bulk substrate, the bonded substrate maintained a low ΔVf and the variation among the measured diodes was extremely small even after applying the highest current density of 1500 A/cm². The investigated number of bar-shaped SSFs within the electrically stressed diodes with more than 1000 A/cm² revealed the possibility that the BPDs existing at deep positions below the epilayer/substrate interface were drastically reduced in the 4H-SiC bonded substrate.