Papers by Author: Siddarth G. Sundaresan

Abstract: Bipolar silicon carbide devices are attractive for high power applications offering high voltage devices with low on-state voltages due to plasma flooding. Unfortunately, these devices suffer from bipolar degradation, which causes a significant degradation of the on-state voltage. To explore the generation of stacking faults, which cause the degradation, the impact of the current density and temperature on bipolar degradation is investigated in this work. The analysis is done by stressing the base-collector diode of 1.2 kV bipolar junction transistors (BJTs) as well as the BJTs in common-emitter mode operation with different current densities at different temperatures.

Abstract: This paper investigates the 10 ms surge current (I_FSM) and single-pulse avalanche energy (E_AS) limits of 1200 V/10 A SiC Schottky rectifiers from several commercial vendors. GeneSiC’s 1200 V/10 A diode recorded maximum I_FSM values of 162 A at T_C=25°C and 135 A at T_C=150°C, which were the highest amongst investigated devices. The diode sustains junction temperatures as high as 910°C during surge current operation, which results in eventual failure of the Aluminum based metallization.

Abstract: A comprehensive investigation of the operating limits and failure modes for 4600 V/7.78 mm² SiC DMOSFETs under unclamped inductive switching (UIS) conditions is presented. Maximum single-pulse avalanche energies (E_AS) as high as 1.07 J (13.75 J/cm²) and avalanche withstand times (t_AV) as high as 71 μs are recorded. The variation of E_AS and t_AV with load inductance (or avalanche current) is quantified. Stability of the key DMOSFET performance characteristics including R_DS,on, V_TH, body-diode, gate/drain leakage currents and terminal capacitances under both single-pulse and repetitive (up to 1000 shots) avalanche conditions are examined. Different failure locations confined within the active area of the DMOSFETs are identified after avalanche failure for either low or high E_AS failed devices and a tentative model to explain the failure physics is presented.

Abstract: Large-area, 7.84 mm² SiC DMOSFETs feature breakdown voltages of 4600 V, specific on-resistance of 17 mΩ-cm² and gate threshold voltage of 2.4 V. The low on-resistance was enabled by an optimized MOS process that resulted in channel mobility as high as 27 cm²/Vs, and oxide breakdown fields in the 10-11 MV/cm range. The key device design and layout parameters were varied to examine the performance versus reliability trade-offs.

Abstract: The current gain stability of a second generation of 1200 V rated SiC Junction Transistors (SJTs) under long-term DC and pulsed current operation is investigated. A 1000-hour long, 200 A/cm² DC current stress results in a ≈ 10% reduction of the current gain (β) during the early stages of the stress test, while the β is perfectly stable for the remainder (>90%) of the stress duration. The same amount of stress charge applied as a pulsed current in lieu of DC current results in similar extent of β degradation for the Gen-II SJTs. The pulsed current stressing is conducted at frequencies ranging from 50 kHz to 200 kHz, at a fixed duty cycle of 0.5.

Abstract: Short-circuit (SC) robustness of 1200 V-rated SiC npn Junction Transistors (SJTs) and commercial power DMOSFETs is investigated. Due to low (2x) overdrive base currents and low short-circuit currents, SJTs demonstrate superior SC capability including: (a) minimum short-circuit withstand time (t_SC) of 14 µs, even at V_DS=1000 V (b) Perfectly stable output and blocking characteristics after 10,000, 10 µs long SC pulses at 800 V, (c) t_SC ≥ 18 µs at 800 V up to (at-least) 175°C base-plate temperatures. In contrast, commercial (Gen-II) 1200 V/80 mΩ SiC MOSFETs exhibit catastrophic failure beyond t_SC = 7 µs at 500 V, and t_SC = 3 µs at 800 V, due to excessive SC currents of > 200 A resulting in junction temperatures in excess of 650°C. The MOSFET’s drain leakage current increases by a factor of 120, and the V_TH reduces by 20%, after 7 µs-long SC pulses at 500 V.

Abstract: 1700 V/20 mΩ SiC Junction Transistors (SJTs) were recently released by GeneSiC with specific on-resistance as low as 2.3 mΩ-cm², and current gain > 100. This paper benchmarks the electrical characteristics of the 1700 V SJTs against two best-in-class Si IGBTs. The SJT features 47% and 49% lower on-state voltage drops than the two Si IGBTs, respectively, with the SJT operating at 175°C, and the IGBTs at 150°C. The conduction power loss of the best Si IGBT is 2.2 times larger than the SJT at 25°C, and 1.6 times larger at 150°C. The leakage currents measured on the best IGBT at 1700 V and 150°C is 0.93 mA, as compared to 200 nA for the SJT at 175°C. As compared to the SJT, 3.6x and 3.3x higher (hard) switching energy losses are measured on the best 1700 V Si IGBT, at 25°C, and 150°C, respectively, when switching at a DC link voltage of 1200 V.

Abstract: Three different turn-off strategies are presented for 6.5 kV class SiC Thyristors. A cathode current of 62 A (284 A/cm²) is successfully turned off by applying a reverse bias of ≈ 30 V to the cathode of a SiC Thyristor. The minimum turn-off time (t_q) for the Thyristor using this forced commutation technique is investigated as a function of cathode current density, reverse gate current and the dV/dt of the re-applied forward (blocking) bias. The Anode Switched Thyristor (AST) turn-off mode is demonstrated at a maximum cathode voltage of 3600 V and 14.5 A (199 A/cm²) of cathode current. A cathode current of 5.5 A (75 A/cm²) is successfully turned off by the gate turn off (GTO) or hard turn-off mode at different temperatures up to 200°C. The high-level lifetime (t_HL) in the thick p-layer is extracted from the hard turn-off waveforms.

Abstract: SiC Junction Transistors (SJTs) with 1900 V Drain-Source breakdown voltages, current gain (h_FE) higher than 120 and low on-resistance of 22 mΩ (3.5 mΩ-cm²) are reported in this paper. SJTs with a pre-stress h_FE of 90 suffer only a 10% reduction of the h_FE after 190 hours under a 200 A/cm² DC current stress at a T_J of 125°C, while a similar stress on earlier generation SJTs resulted in over 25% h_FE reduction in only 25 hours. SJT die with pre-stress h_FE in the range of 120-125 show absolutely no current gain degradation even after a 300°C/ 2 hour stress at 60 A/cm² DC drain current.

Abstract: SiC npn Junction Transistors (SJTs) with current gains as high as 132, low on-resistance of 4 mΩ-cm², and minimal emitter-size effect are demonstrated with blocking voltages > 600 V. 2400 V-class SJTs feature blocking voltages as high as 2700 V combined with on-resistance as low as 5.5 mΩ-cm². A significant improvement in the current gain stability under long-term high current stress is achieved for the SJTs fabricated by the high gain process.