Papers by Author: Suguru Saito

Abstract: We investigated the effect of Si wet etching on the vertical step at wafer edge. We found that the concave-convex shape appeared at the wafer edge after Si etching by the Atomic Force Microscopy analysis. From the liquid simulation and the detailed evaluation of Si etching rate, we revealed that the concave-convex shape was formed by the distribution of the fluid velocity at the wafer edge.

Abstract: The microminiaturization of semiconductor devices has made it necessary to control the wet etching process on the nanometer order. It is therefore extremely important to understand wet etching reactions in the nanoscale region of solid-liquid interfaces, in order to assist in optimizing process conditions to satisfy the severe demand for semiconductor devices. Simulations performed to analyze the behavior of liquid molecules in the nanoscale region have been reported ^[1], but there have been few reports of detailed experimental results. We here report detailed experimental results on the wet etching behavior of SiO₂ film in the nanoscale region between Si materials.

Abstract: High-k gate dielectrics and metal gate electrodes have become essential for emerging device technologies because they enable the continuous scaling down of devices while maintaining a high performance [. However, since they are composed of novel metallic elements that have never before been used in conventional processes, special care must be taken when handling these materials in the production line. In particular, cross-contamination that occurs due to transporting contamination via processed wafers can cause serious problems such as deterioration of device properties and yield loss [. The process of cleaning the backside and bevel of a wafer is now increasingly important for avoiding these problems. To date, there has been no detailed evaluation of contamination removal on various films performed for elements such as hafnium, which is one of the key elements in high-k/metal gate technologies. In this study, we evaluated hafnium contamination on three types of wafer surface after the cleaning process and investigated the cause of different residual amounts of hafnium contamination on the different wafers.

Abstract: Recently, plasma-less gaseous etching processes have attracted attention for their interesting etching properties. Previously, we reported on the etching properties of theses processes for various kinds of oxides and revealed that they reduce the etch rate of the chemical-vapor-deposited (CVD) oxides more than the conventional wet etching process does [1]. Our results also revealed that depressions called divots in the CVD oxide of the shallow trench isolation (STI) became smaller in size by substituting a plasma-less gaseous etching process for the conventional wet etching process. In semiconductor manufacturing, many processes are used to remove oxides damaged during ion implantation or reactive ion etching on the device surface. Therefore, it is very important to understand the etching properties of plasma-less gaseous etching processes for damaged oxides as well as those for other kinds of oxides. In this report, we evaluate the etching properties of one particular plasma-less gaseous etching process for oxide films damaged during the ion implantation process under various conditions and discuss the mechanism of interesting etching properties for the damaged oxides.