Papers by Author: T. Paul Chow

Abstract: We report an anomalous reverse-recovery (RR) of the body diode in a 3.3 kV 4H-SiC superjunction (SJ) DMOSFET: at 77 K, Q_RR,sp increases by 1.4×–3.5× versus room temperature and 5× versus 195 K, and J_PR increases by >2×, while t_RR changes by only <30ns. A clear dependence of Q_RR,sp on the ramp rate at 77K indicates the Q_RR,sp is not due to additional depletion charge. Current-controlled negative resistance (CCNR) is also observed solely for the SJ body diode at 77K. The voltage waveforms strongly suggest the additional Q_RR,sp is due to dynamic breakdown of the SJ due to transient charge imbalance of the pillars caused by delayed hole emissions of the deep acceptors. The anomalous behavior is qualitatively reproduced in simulation. We also benchmark a 3.3kV Charge Balance (CB) 4H-SiC DMOSFET along with the SJ device from 77–423 K using an inductive double-pulse test. For T > 77 K the switching for both devices is dominated by the depletion capacitance (weak Q_RR,sp dependence on the ramp rate): the SJ device turns off faster (t_RR = 0.3–0.8× CB), is snappier (t_B/t_A = 0.23–0.56× CB), and shows larger J_PR (1.8–2.8× CB) while recovering less charge (Q_RR,sp = 0.4–0.8× CB). The CB device shows the expected increase of Q_RR,sp with temperature and only modest t_RR temperature variation. Overall, the CB device provides softer, predictable RR without a cryogenic anomaly, whereas SJ delivers the shortest t_RR above 77 K but exhibits the 77 K anomalous increase and is consistently snappier.

Abstract: We generalize a recent Si P-i-N reverse-recovery (RR) model to more accurately capture 4H-SiC diode behavior by adding deep-acceptor-limited anode injection, strong recombination (due to >100x shorter optimized high-level lifetimes compared to Si), and improved modeling of the depletion layer dynamics. Closed-form expressions for the growth of the depletion layer are derived, enabling analytical estimates for Q_RR, t_RR, and J_PR. The model is validated against Sentaurus RR simulations of optimized 4H-SiC P-i-N diodes spanning BV = 6–17kV and di/dt = 10 A/µs–10 kA/µs, achieving an average reduction in error of >90% for estimations of key switching performance parameters (Q_RR, t_RR, J_PR). By correctly capturing the dependence of Q_RR on di/dt, the model enables better estimates for the high-level lifetime (τ_HL) directly from the RR waveforms. The differential form enables straightforward utilization of the model to analyze non-idealized RR waveforms. Overall, the generalized model reveals a more favorable Q_RR–V_F trade-off than implied by the unmodified Si model and improves first-order device optimization prior to full design.

Abstract: We have demonstrated an integrated 3.3 kV 4H-SiC vertical planar bidirectional (BD) conventional (Conv) power DMOSFET in common-drain (CD) configuration using two commercially available power DMOSFET dies and study its operation down to 77 K (-196 °C) to evaluate its cryogenic static and switching performance. The BD conduction and blocking are achieved down to 77 K. The measured specific on-resistance (R_ON,sp) of the BD MOSFET at room temperature (RT) is 26 mΩ-cm², approximately twice that of the unidirectional device. It increases by 54% when cooled to 77 K due to a substantial increase in channel and possibly JFET on-resistance components. In addition, the extracted specific switching losses (E_ON,sp and E_OFF,sp) increases by 33% (13%) at 195K (–77 °C) and by 83% (88%) at 77 K, relative to their RT values. These increases are primarily attributed to the substantial rise in R_ON,sp at 77 K. As a result, the implemented BD Conv DMOSFET exhibits degradation in both on-state and switching performance under cryogenic operation, driven mainly by the significant increase in channel and JFET resistance components.

Abstract: Extensive experiments and simulations indicate that Single-Event ion bombardment Effects (SEE) can trigger a Single-Event Burnout (SEB) in 4H-SiC vertical power devices at lower than half of the rated breakdown voltage. This paper investigates the SEB robustness of a 1.2kV 4H-SiC lateral RESURF MOSFET using a 3-D electrothermal device simulator (Sentaurus) with a reported heavy ion model based on high-fidelity radiation data. The maximum V_SEB/BV_rate ratio of 0.67 is 2.2 times higher than the reported V_SEB/BV_rate ratio of 0.3 for a 4H-SiC vertical DMOSFET with the same voltage rating. The reason is due to the reduced surface field at the drain terminal and the orthogonality of the heavy ion and impact ionization paths, resulting in less efficient excess carrier generation. This highlights the potential of lateral power devices for use in radiation-hardened environments.

Abstract: By using 4H-SiC packaged Charge-Balanced (CB) MOSFET, we have experimentally demonstrated a 3.3kV 4H-SiC common-drain bidirectional (BD) CB power MOSFET and measured its static and dynamic characteristics compared to its unidirectional counterpart. We show that the BD CB MOSFET conducts and blocks at the first and third quadrants with the appropriate gate bias with an on-state resistance double its unidirectional counterpart, while its switching energies are 12 (19) and 34 (12) mJ/cm² for BD CB MOSFET (UD CB MOSFET).

Abstract: We quantitively compare the static and dynamic performance for high-voltage SiC bidirectional (BD) conventional and superjunction (SJ) DMOSFETs by using 3D TCAD simulations. We extract the specific on-resistance (R_ON,sp) and the total specific switching charge (Q_T,sp), which is a sum of the specific gate charge (Q_G,sp) and drain charge (Q_DS,sp) to quantify both the static and switching characteristics respectively. We also develop a new Figure-of-Merit (FoM), which is the product of R_ON,sp . Q_T,sp, to evaluate the overall performance. We show that the high-voltage 4H-SiC BD SJ DMOSFET has the best FoM with substantial (>58%) improvement, compared to the BD conventional DMOSFETs, which increases with increasing breakdown voltage.

Abstract: We evaluate and compare the static and dynamic performances of four different 4H-SiC power MOSFETs (Conventional DMOS and UMOS, Superjunction (SJ) DMOS and UMOS FETs) from 0.6 to 10kV. The static on-state performance is determined by analytically calculating the specific on-resistance (R_ON,sp), while the dynamic switching performance is determined by extracting the specific gate charge (Q_G,sp) and switching energy loss per cycle (E_sw,cycle) using 2D device simulations. It has been found that the SJ UMOS FET exhibits at least a 31% (up to 53% at 0.6kV) reduction in the R_ON,sp · Q_G,sp Figure-of-Merit (FoM) compared to the SJ DMOS FET within the breakdown voltage rating range studied.

Abstract: We determine the effective critical breakdown field for 4H-SiC superjunction (SJ) devices and compare it to their conventional counterparts. Also, we investigate its dependence on SJ device structural parameters, such as drift layer thickness (t) and pillar width (W). In 4H-SiC SJ devices, the effective critical breakdown field was found to be around 30% lower than that of conventional devices owing to their longer ionization paths. In particular, the effective critical electric field varies as ξ_cr α t^-1/10 and ξ_cr α t^-1/6 for 4H-SiC SJ and conventional devices respectively but independent of pillar width and doping concentration for high aspect ratio devices (t/W > 10).

Abstract: MeV level aluminum implants into 4H-SiC were performed as part of superjunction diode fabrication. Measurement of resistance test structures produced resistivities well above expected values with large decreases at elevated temperatures. Capacitance-voltage measurements indicate a high activation rate of the implanted aluminum. Temperature dependent Hall measurements produce reasonable hole mobilities with acceptor ionization energies of approximately 330meV, well above the 200meV expected for low concentration aluminum doping in 4H-SiC.

Abstract: We compare the failure mechanism and performance of a silicon carbide (SiC) semi-superjunction (semi-SJ) power DMOSFET against pure SJ and conventional DMOSFET when struck by a single heavy ion. The Single-Event Burnout (SEB) failure mechanism was identified as the thermal runaway from second breakdown resulting in mesoplasma formation. The semi-SJ design shifts the mesoplasma location from the drift/substrate interface seen in the control device structures to a location along the center of the P-pillar and closer towards the DMOSFET surface, thus significantly improving the SEB threshold voltage (V_SEB). The V_SEB varies with pillar width and ratio of pillar thickness to drift layer thickness. A maximum value of V_SEB is reached when the pillar to drift layer ratio is 0.9 and the pillar width is 2.4 μm. The semi-SJ SEB/breakdown voltage ratio is 100% and 13% higher than the pure SJ and conventional DMOSFET, respectively. Using a new Figure of Merit (FoM), which accounts for the tradeoff between V_SEB and on-state performance, we find that the SiC semi-SJ DMOSFET achieves a FoM that is 1.8 and 8 times higher than SJ and conventional DMOSFET, respectively, making the semi-SJ a competitive candidate for radiation hardened applications.