Papers by Author: T. Paul Chow

Abstract: We have characterized gate capacitive and conductive behaviors of commercial Si and 4H-SiC vertical MOSFETs that have never been reported previously. The characteristics and possible physical reasons are determined and corroborated with device simulations. The measurements were carried out on different 1200V 4H-SiC MOSFETs from several vendors by impedance analyzer. Typical C-V characteristics of gate-controlled diodes are observed in those MOSFETs, while several conductance peaks are also captured in G-V measurements. These conductance peaks, reproduced with numerical simulations, are not necessarily related to the behavior of any interface states at the gate oxide/ 4H-SiC interface.

Abstract: We have determined, using the Conductance-Frequency (G-ω) Technique, the creation and annihilation process of the 3 interface trap levels (OX, OX’ and NI levels) previously reported [1-3] and their possible correlation to inversion electron trapping and mobilities. The measurements were carried out on various 4H-SiC Metal Oxide Semiconductor (MOS) capacitors that have been processed using several gate oxide processes [2,5,6]. Our analysis focus on the correlation of the interface trap levels on the process conditions so as to first understand and then control their formation.

Abstract: We have performed detailed dynamic switching measurements for 3kV 4H-SiC Charge-Balanced (CB) junction barrier Schottky (JBS) diodes [1,2] and studied their dependence on device design parameters. We have done forward and reverse recovery characterizations and found unusual switching characteristics in these CB-JBS diodes. These switching characteristics are explained based on the design and layout of the devices.

Abstract: Using commercially available SiC MOSFET dice, bidirectional MOSFETs were assembled and their electrical performance was tested. With proper gate biasing, the pair is capable of blocking at or near the rated value of the component MOSFETs in each direction. The pair conducts in both directions with an on-state resistance comparable to the sum of the constituent device resistances. With optimization of the component devices, this configuration promises to improve bidirectional switch performance beyond that of the simple assembled pair.

Abstract: The electrical behavior of silicon carbide charge-balance (CB) Schottky/JBS diodes is examined. Based on the observed electrical characteristics, a subcircuit SPICE model for the experimental devices is proposed and validated against the data. The proposed model consists of a standard SPICE diode with custom parameters along with a network of discrete resistive and reactive subcircuit elements required to replicate the complex static and dynamic behavior of the experimental devices. With proper selection of component values, static, dynamic, and temperature-dependent device behavior are well modelled from room temperature to 150°C.

Abstract: This paper describes the mechanisms behind the failure of silicon carbide (SiC) Power MOSFETs (metal oxide semiconductor field effect transistors) when struck by a heavy ion. The modeled device is designed to simulate a commercially available 1200 V power MOSFET under the strike of a silver ion with a Linear Energy Transfer (LET) of 46 MeV-cm²/mg commonly used in single event effect (SEE) testing. The device is shown in simulation to fail near 500 V, which is in close agreement to experiments. The failure occurs near the interface between the epitaxial layer and the substrate layer due to the rapid increase of the electric field in that region and destruction of the device from impact ionization. Two improved designs were proposed and investigated that would help to mitigate the electric field in these regions and improve the device’s tolerance to single-event burnout (SEB). The new designs increased the voltage at which SEB occurs from 500 V to over 900 V and increased the specific on-resistance (R_on,sp) by only 5%.

Abstract: We have studied capacitance mode Deep Level Transient Spectroscopy (DLTS) of five 4H-SiC Schottky diode and PiN diode designs. Comparing with previous DLTS studies, we have identified four traps levels, Z_1/2, EH₁, EH₃ and EH₅. Additionally, a new trap level, EH₁, is prominent in blanket Al⁺ and B⁺ high-energy implanted samples but less so in mask-implanted samples. Al⁺ implantation increases EH₃ (associated with silicon vacancy) and EH₅, while B⁺ implantation significantly reduces EH₃. The Z_1/2 peak (associated with carbon vacancy) is reduced to very low levels after B⁺ and Al⁺ implantation.

Abstract: We have evaluated the specific on-resistance (R_on,sp) vs. BV trade-off limit of vertical superjunction (SJ) devices for 4H-SiC and 2H-GaN using a previously published analytical model. In addition, we have identified and replaced some unsuitable assumptions found in previous work. Our results show that the R_on,sp of vertical SJ devices is between one and four orders of magnitude lower than the 1D limit of 4H-SiC and 2H-GaN devices at same breakdown voltage, but significantly higher than the previous projected limit for 4H-SiC. The optimized specific on-resistance for SJ devices is lower than that for conventional devices by factors of 3X and 100X for 1kV and 10kV devices respectively. These figures are, however, 25X higher than previous projections.

Abstract: 1200V SiC power MOSFETs of various cell geometries are modeled in Synopsis Inc. Sentaurus TCAD. The impact of cell geometry on switching loss is studied by comparing the turn-on and turn-off losses using refined calculation methods. Under optimum circuit conditions, two different novel unit cell designs each achieve lower switching losses than conventional designs. For all the designs, lossless turn-on is impossible but lossless turn-off is achievable under circuit and biasing conditions that produce sufficiently rapid gate slew.

Abstract: We present a comparative study of the electrical characteristics of different 1200V commercial SiC power MOSFETs at cryogenic temperatures down to 77 K. As compared to conventional silicon power MOSFETs, SiC MOSFETs show very different operating characteristics at low temperatures which is due to unique material and design parameters used in SiC MOSFETs. Of particular interest is a non-linear mixed triode/pentode-like I-V characteristic exhibited by all SiC MOSFETs at 77 K, which is demonstrated to be due to short channel effects in the constituent JFET.