Papers by Author: Takashi Shinohe

Abstract: We have fabricated the lateral MOSFETs on (11-20) and (1-100) faces and have compared the properties between these faces with various gate oxide processes. It has been demonstrated that (11-20) and (1-100) faces show comparable electrical properties with nitridation treatment on the gate oxide. Our result indicates that both faces exhibit the similar trend of the mobility vs. D_it. Furthermore, it has been shown that NO POA is beneficial to both faces in achieving high channel mobility and suppressed V_t instability.

Abstract: Silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The effect of current spread layer (CSL) structure was studied. 1.9 mm × 1.9 mm DIMOSFETs were characterized from room temperature to 200°C. At room temperature, the specific on-resistance of this MOSFET was 14.8 mΩcm² at a gate bias of 20 V and a drain voltage of 0.5 V. The blocking voltage of this MOSFET was 3300 V. At 300 °C, the specific on-resistance increased from 14.8 mΩcm² to 83.9 mΩcm² and the threshold voltage decreased from 5.3 V to 3.4 V.

Abstract: We have studied gate oxide processes for SiC trench MOSFETs. It is demonstrated that nitridation of gate oxide is effective to suppress the variation of channel mobility depending on channel plane orientation and substrate off-angles. In addition, improved channel mobility has been obtained by the combined process of NH₃ and N₂O POA.

Abstract: In this paper, we found origin of V_F degradation of SiC bipolar devices other than a basal plane dislocation (BPD) in the SiC substrate. A V_F degradation of the 4H-SiC PiN diodes with low-BPD wafers was evaluated and its origins were discussed. Some diodes suffered V_F degradation, even though they were fabricated on BPD-free area. PL mapping, TEM image, and optical observation after KOH etching showed that there were Shockley stacking faults and combined etch-pits arrays, which were presumed to be caused by the device process.

Abstract: The causes of extrinsic failures in time-dependent dielectric breakdown characteristics of gate oxide on C-face of 4H-SiC are examined by comparing breakdown points of tested gate oxides with the images of X-ray topography and those of differential interference contrast microscopy. We have concluded as follows: (1) surface morphological defects that originate from threading screw dislocations degrade reliability of gate oxides. (2) These surface defects are not necessarily found on every wafer. (3) Crystallographic defects are not killer defects of MOSFET per se.

Abstract: 1.2 mm × 1.2 mm and 2.7 mm × 2.7 mm silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. 1.2 mm × 1.2 mm DIMOSFETs were characterized from room temperature to 150°C. At room temperature, the specific on-resistance of this MOSFET was 5.7 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The blocking voltage of this MOSFET was 1450 V based on the avalanche current. At 150 °C, the specific on-resistance increased from 5.7 mΩcm2 to 9.1 mΩcm2 and the threshold voltage decreased from 4.9 V to 4.1 V. The blocking voltage increased from 1450V to 1500V. 2.7 mm × 2.7 mm DIMOSFETs were also characterized at room temperature. They showed a specific on-resistance of 8.0 mΩcm2 at a gate bias of 20 V and a drain voltage of 1 V. The blocking voltage of this device was 1550 V, which was determined by the avalanche current. The time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) characteristics of 180 μm × 180 μm MOS capacitor were estimated. At room temperature (RT), TZDB was 9.3 MV/cm and the charge to breakdown value of 63% cumulative failure (Qbd) was 72 C/cm2. The temperature dependence of Qbd measurements showed that it deceased from 72 C/cm2 at RT to 14 C/cm2 at 250 °C. Switching characteristics of 1.2 mm × 1.2 mm DIMOSFETs were obtained by the double-pulse measurements. The turn-on time and the turn-off time were 36 nsec and 53 nsec, respectively.

Abstract: SiO2/4H-SiC interfaces are examined by high-resolution transmission electron microscopy (HRTEM), high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM), and spatially resolved electron energy-loss spectroscopy (EELS). HRTEM and HAADF-STEM images of SiO2/4H-SiC interfaces reveal that abrupt interfaces are formed irrespective of the fabrication conditions. Transition regions around the interfaces reported by Zheleva et al. were not observed. Using EELS, profiles of the C/Si and O/Si ratios across an interface were measured. Our measurements did not reveal a C-rich region on the SiC side of the interface, which was reported by Zheleva et al.

Abstract: Silicon carbide Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The DIMOSFETs were characterized from room temperature to 250°C. At room temperature, they showed a specific on-resistance of 4.9 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The specific on-resistance taken at a drain current (Id) of 260 A/cm2 was 5.0 mΩcm2. The blocking voltage of this device was higher than 1360 V at room temperature. At 250°C, the specific on-resistance increased from 5.0 mΩcm2 to 12.5 mΩcm2 and the threshold voltage determined at Id = 26 mA/cm2 decreased from 5.5 V to 4.3 V.

Abstract: This paper discusses the issues regarding reliability of large-area (up to 25mm2) gate oxide on the C-face of 4H-SiC. We have shown that the TDDB characteristics of large-area gate oxide improved by separating gate oxidation processes into oxide growth by dry-oxidation and successive interface control by anneal in N2O ambient or that by wet-oxidation followed by anneal in H2 ambient. In particular, dry-oxidation followed by anneal in N2O ambient for interface treatment (dry+N2O process) is effective for the suppression of the random failure in TDDB characteristics. The estimated lifetime of gate oxide of less than 9mm2 by the dry+N2O process is six-digits larger than 30 years. In the case of the TDDB characteristics of 25mm2 gate oxide grown by the dry+N2O process, the initial and random failure in TDDB characteristics is dominant. However, even in this case, we have confirmed that the evaluated lifetime of 25mm2 gate oxide is more than 30 years. In order to clarify the mechanism of the degradation of the TDDB characteristics of large-area gate oxide, we examined the effect of the surface defect on the TDDB characteristics by observing the surface of each broken MOS capacitor after the TDDB test. We have found following results. (1) The initial failures in TDDB characteristics are mainly due to surface defects such as “down fall”, “comet”, and “triangular defect”. (2) The footprints of random failure do not correspond to the positions of smaller surface defects such as “bump”. Finally, we have found that the quality of the epitaxial layer affects random failure rate in the TDDB characteristics of large area gate oxide; the random failure in the TDDB characteristics of 25mm2 gate oxide on epitaxial layer grown by a certain epitaxial vendor is almost suppressed. However, the cause of the difference in TDDB characteristics is not identified.

Abstract: The influences of processing and material defects on the electrical characteristics of large-capacity (approximately 100A) SiC-SBDs and SiC-MOSFETs have been investigated. In the case of processing defects, controlled activation annealing is the most important factor. On the other hand for material defects, the number of epitaxial defects must be decreased to zero for both SBDs and MOSFETs. The dislocation defects in SiC wafers are dangerous for the breakdown voltage of MOSFETs. However, they are not killer defects. If the epitaxial defect density is sufficiently low and the dislocation density is in the order of 10000cm-2, the long- term reliability of the gate oxide at the electric field of 3MV/cm can be guaranteed.