Papers by Author: Tetsuya Miyazawa

Abstract: Application of highly N-doped buffer layers or a (N+B)-doped buffer layer to PiN diodes to suppress the expansion of Shockley stacking faults (SSFs) from the epilayer/substrate interface was studied. These buffer layers showed very short minority carrier lifetimes of 30–200 ns at 250°C. The PiN diodes were fabricated with buffer layers of various thicknesses and were then tested under high current injection conditions of 600A/cm². The thicker buffer layers with shorter minority carrier lifetimes demonstrated the suppression of SSFs expansion and thus that of diode degradation.

Abstract: Epitaxial growth of 4H-SiC with intentional V or Ti doping was performed to obtain short minority carrier lifetimes, using VCl₄ or TiCl₄ as the doping sources. The doping efficiencies and quality of the epilayers were compared for H₂+SiH₄+C₃H₈ and H₂+SiH₄+C₃H₈+HCl gas systems. The addition of V or Ti in highly N-doped epilayer demonstrated very short minority carrier lifetimes of 20-30 ns at 250°C.

Abstract: An epitaxial growth technique for 4H-SiC with B doping was developed to control the carrier lifetimes of the epilayers. A linear relationship was observed between the B doping concentration and the flow rate of tri-ethyl-boron, which was used as the B doping source. A room temperature photoluminescence spectrum of a N-and B-doped epilayer showed a broad B-related peak at 2.37 eV instead of a band-edge luminescence, which indicates that the carrier recombination path was changed by the B doping. The minority carrier lifetime decreased (< 30 ns at 250°C) with increasing B doping concentration. The thermal stability of the short carrier lifetime was compared with a conventional carrier lifetime reduction method, namely an electron irradiation technique. After thermal annealing at 1700°C, the carrier lifetime of the electron irradiated epilayer recovered while that of the B-doped epilayer remained, indicating that the carrier lifetime controlled by the B doping technique was more stable against the thermal processes.

Abstract: This paper reports on recent advances in 4H-SiC epitaxial growth toward high-throughput production of high-quality and uniform 150 mm-diameter 4H-SiC epilayers by enhancing of growth rates, improving uniformity and reducing defect densities. A vertical single-wafer type SiC epitaxial reactor is employed and high-speed wafer rotation is confirmed as effective, not only for enhancing growth rates without increasing the source gas supply but also improving thickness and doping uniformities. The current levels of reducing particle-induced defects, in-grown stacking faults, basal plane dislocations and the Z_1/2 center (carbon vacancies) are reviewed.

Abstract: Thick multi-layer 4H-SiC epitaxial growth was investigated for very high-voltage Si-face p-channel insulated gate bipolar transistors (p-IGBTs). The multi-layer included n⁺ buffer, p⁺ field stop, and thick p^- drift layers. Two processes were employed to enhance the carrier lifetime of the p^- drift layer: carbon ion implantation/annealing and hydrogen annealing, and the enhanced carrier lifetime was confirmed by the open-circuit voltage decay measurement. Using the grown thick multi-layer 4H-SiC, simple pin diodes were fabricated instead of p-IGBTs to demonstrate efficient conductivity modulation in the thick p^- drift layer. While the on-state voltage was high at room temperature, it decreased significantly at elevated temperatures, and attained 3.5 V at 100 A/cm² at 200°C for the diode with the carrier lifetime enhancement processes, indicating sufficient conductivity modulation.

Abstract: This work reports on description and application of a new Photoluminescence (PL) Imaging technique for in-grown stacking fault (SF) characterization and identification on 4H-SiC epilayers. The purpose of this technique is to make a spectroscopic picture from a collection of PL imaging picture taken at different output wavelengths in order to both display the shape and an approximation of the maximum PL intensity wavelength at room temperature (RT) of the characterized SF. This is why we called this technique “PL Imaging Spectroscopy”. Five types of SFs have been observed and compared to PL spectra collected at RT and 10K.

Abstract: The epitaxial growth of thick multi-layer 4H-SiC to fabricate very high-voltage C-face n-channel IGBTs is demonstrated using 3-inch diameter wafers. We employ an inverted-growth process, which enables the on-state voltage of resultant IGBTs to be reduced. Furthermore a long minority carrier lifetime (> 10 μs) and a low-resistance p⁺ epilayer can reduce the forward voltage drop of the IGBTs. The small forward voltage drop is demonstrated particularly at high temperatures by fabricating and characterizing simple pin diodes using the epi-wafer.

Abstract: This paper introduces our recent challenges in fast 4H-SiC CVD growth and defect reduction. Enhanced growth rates in 4H-SiC epitaxial growth by high-speed wafer rotation and in a high-temperature gas source method promoting SiC bulk growth by increasing the gas flow velocity are demonstrated. Trials and results of deflecting threading dislocations by patterned C-face 4H-SiC epitaxial growth are also shown.

Abstract: The electrical characteristics of 4H-SiC pin diodes with 8H-type in-grown stacking faults are investigated. The pin diodes have epilayers with low Z_1/2 center concentration formed by using the carbon implantation process. The forward voltage drops of the diode with 8H-type in-grown stacking faults are larger than those of the diode without a 8H-type in-grown stacking fault. At room temperature, the differential on-resistance of the pin diode with 8H-type in-grown stacking faults is larger than the value calculated from donor concentration in the drift layer by using the current transportation model of the unipolar device. Meanwhile, the differential on-resistances of the pin diode with 8H-type in-grown stacking faults decrease with an increase in temperature and become smaller than the calculated value at temperature of more than 200 °C.

Abstract: The forward voltage drops of pin diodes with the carbon implantation process or thermal oxidation process using a drift layer of 120 μm thick are around 4.0 V and are lower than those with the standard process. The reverse recovery characteristics of diodes with the standard process or carbon implantation at room temperature show almost the same tendency. In the reverse recovery characteristics at 250 oC, pin diodes with carbon implantation process, however, have the longer reverse recovery time than those with the standard process. These characteristics indicate that a recombination path other than the bulk carrier lifetime, such as the interfaces or the surface recombination, becomes dominant in the reverse recovery characteristics at room temperature.