Papers by Author: Yasunori Tanaka

Abstract: In this study, we conducted in-situ measurements on a SiC JFET operational amplifier operating under gamma-ray irradiation. It shows that the radiation did not affect the output waveform or voltage gain, but shifted the output offset voltage. This shift may result mainly from holes generated by irradiation and trapped in the oxide layer, which modified the I-V characteristics of the level-shifting diodes. It can be compensated by applying bias voltage, and it may also be prevented by optimizing the diode structure and/or circuit topology.

Abstract: Currently, silicon carbide (SiC) is widely recognized as a wide bandgap semiconductor, with expanding applications in harsh environments, such as high temperature and radiation exposure. In this study, we fabricated a planar structure 4H-SiC gate-all-around junction field-effect transistor (JFET), wherein the channel region is formed through ion implantation at varying doses. We successfully produced both normally-on and normally-off JFETs. Moreover, we constructed a JFET commonsource amplifier. The amplifiers achieved a maximum gain of -226.7 (47.1 dB) at a supply voltage of V_DD = 30 V.

Abstract: A novel substrate of 4H-SiC bonded substrate is expected to solve issues such as decreasing the on-resistance, which has attracted much attention. Therefore, several studies have been conducted on the use of bonded substrates. In this study, we fabricated a DMOSFET on a bonded substrate and compared its static and dynamic characteristics with those on a single-crystal substrate. Consequently, the on-resistance of the DMOSFET fabricated on a bonded substrate was lower than that on a single-crystal substrate owing to the low resistivity of the polycrystalline substrate. Also, reverse recovery loss of the DMOSFET fabricated on a bonded substrate was lower than that on single-crystal substrate at high temperature due to low carrier lifetime in a drift layer. Additionally, we observed that the DMOSFET fabricated on a bonded substrate did not generate bipolar degradation despite the application of a forward-current stress of over 1500 A cm^-2. According to these results, we expected that the carrier lifetime in both drift layer and transfer layer was decreased on a bonded substrate.

Abstract: The avalanche robustness of 430 V SiC avalanche diodes at high temperatures is investigated. The UIS test was performed with fixed avalanche time in order to avoid the effect of a thermal diffusion time on an avalanche energy. It is found that the avalanche energies at 25 are 10.5 J/cm² for and 12.7 J/cm² for while those at 170 are 8.02 J/cm² and 9.96 J/cm², respectively. Their temperature coefficients are about-0.018 J/cm²K, which are much smaller than those of typical SiC-MOSFETs, indicating that the SiC diodes maintain great avalanche robustness even at high temperatures.

Abstract: Silicon carbide junction field effect transistors (SiC JFETs) were irradiated with gamma-rays up to 9 MGy (H₂O). With increasing dose, apparent shift of drain current-gate voltage (I_D-V_G) curves to negative voltage side as observed for SiC metal oxide semiconductor (MOS) FETs did not take place. No significant difference is observed between drain and gate leakage currents of irradiated JFETs. This strongly indicates that defects as leakage paths were introduced into not bulk region but the interface between bulk and the passivation layer of SiO₂. While, the transfer characteristics including threshold voltage and transconductance were slightly changed compared with the pristine sample. After drain voltage (V_D) was abruptly applied to 6 V, I_D at V_G= 0 V increased slowly as a function of time. This indicates that variation of transfer characteristics is attributed to capture and emission process at defects generated in channel region.

Abstract: Stress tests were conducted for the cascode switch using the SiC buried gate static induction transistor (SiC-BGSIT). The stress of the reverse overshoot voltage was periodically applied to the pn junction between the gate terminal and source one in the BGSIT in the cascode with pulses of 40kHz for 202 hours. This simulates the stress which can be occurred in the channel region of the BGSIT during the turn-off and turn-on operation with a parasitic inductance in the interconnection of the cascode package. The result of the stress tests has revealed that there is no significant difference between the electrical characteristics of the BGSIT cascode sample before the stress and those after the stress. Thus, the BGSIT cascode can guarantee high reliability against the stress. The result from the drain current DLTS suggests that no deferent kind of defect is created in the channel region of the BGSIT by the stress.

Abstract: A p-n junction diode with mesa structure by silicon carbide (SiC) has been developed to utilize the avalanche breakdown in an excessed reverse bias condition to clamp the surge voltage in switch-mode power supplies. Static voltage-current correlation by pulsed reverse voltage has been measured. The increase of the breakdown voltage was measured to be 32 volts with increased current density up to 3900 A/cm². The operational performance in suppressing the surge voltage in a step-down DC/DC converter has been evaluated. A superior performance in suppressing the surge voltage by the SiC p-n junction diode has been confirmed. It was also found that a resonant oscillation induced during clamping period limits the performance. By a circuit analysis with an equivalent circuit model, it was found that a parasitic wiring inductance between the diode and switching element induces the resonance. It was also found that a promising way to mitigate the disturbing effect is to minimize the inductance.

Abstract: 4H-SiC and SOI substrates were bonded by SiO₂-SiO₂ direct bonding method with diluted HF solution (0.5 wt.%). After the bonding process, the handle layer and the BOX layer of the SOI substrate were etched by TMAH solution, and finally the silicon active layer with a thickness of 1.5 μm was remained on the 4H-SiC substrate. Using this silicon layer, Si photodiodes on 4H-SiC for the radiation hardened image sensors were fabricated and demonstrated.

Abstract: Oxidized both silicon-face (Si-face) and carbon-face (C-face) wafers with various post-oxidation-annealing conditions were measured by scanning nonlinear dielectric microscopy (SNDM) and method for evaluating SiO₂/SiC interface quality using SNDM was investigated. We found that the normalized standard deviation of SNDM image was good parameter to evaluate SiO₂/SiC interface of Si and C-face. SNDM measurement does not need electrode fabrication to measure C-V curve, but needs just scan on the oxidized wafer with conductive tip, which is easier and quicker. This technique enables us to quickly examine the effect of variation of process parameters in MOS fabrication and to effectively reduce the time needed for R&D cycle.

Abstract: A new technique for local deep level transient spectroscopy (DLTS) imaging using super-higher-order scanning nonlinear dielectric microscopy is proposed. Using this technique, SiO₂/SiC structure samples with different post oxidation annealing (POA) conditions were measured. We observed that the local DLTS signal decreases with POA levels, which agrees with the well-known phenomena that POA reduces trap density. Furthermore, obtained local DLTS images had dark and bright areas, which is considered to show the trap distribution at/near SiO₂/SiC interface.