Papers by Author: Yong Soo Choi

Abstract: As a design rule of memory devices is scaled down to sub-100 nm, shallow trench isolation (STI) technology is faced with gap-filling problem in case of CVD oxide and O3-TEOS oxide processes. To overcome the gap-filling problem, a perhydropolysilazane (PHPS) based spin-on dielectric (SOD) has been implemented for nanoscale devices because of self-planarization and excellent gap-filling property [1]. However, the stability of the SOD has been concerned about because it has relatively softer and more porous than conventional HDP oxide. In this paper, we report the effect of wet oxidant treatment on the stability of the SOD for STI gap-filling.

Abstract: Ceria based slurries with and without PVP were prepared for the polishing of patterned and blanket wafers. The changes in the cross-sectional profiles of the oxide as a function of the polishing time and surfactant concentration were analyzed, in order to understand the mechanism by which the step height of the oxide is reduced during the CMP process. The reduction in the thickness as a function of the polishing time varied with the PVP surfactant concentration in the patterned wafer. When the surfactant concentration was increased to 0.8wt%, the material removal rate of oxide in the patterned wafer approached a maximum. The maximum removal rate observed at a surfactant concentration of 0.8wt% was explained by the competing effects of the increasing number of active particles and the increasing thickness of the viscous layer due to the addition of surfactant.