Papers by Keyword: 3C-SiC

Abstract: 3C-SiC with a moderate band gap and a large electron affinity is expected to have superior long-term stability against performance degradation. We have fabricated Al-gate MOS diodes in 3C-on-4H-SiC and 4H-SiC regions on a simultaneous lateral epitaxy (SLE) wafer. Here, evaluation results of their high-frequency differential capacitance-voltage (C-V) characteristics are reported and, from suggested band diagrams, carrier transport involved in the phenomena are considered. In the case of n^--type 3C-on-4H-SiC MOS diode, increase in capacitance due to fast modulation in the inversion layer charge (hole) concentration can be confirmed in the negative bias below-5 V. 2-dimensional hole gas (2DHG) is considered at the Si-face 3C/4H heterointerface negatively charged by spontaneous polarization and is expected to be an effective supply source of holes. Especially in the case of p-type 3C-on-4H-SiC MOS diode, it is considered that injection of holes from neutral p-type region into the heterointerface induces compensation of the fixed charges and lowering of the electron barrier at conduction band, and then, electron injection through the barrier causes the fast response of inversion-layer modulation. Appearance of the larger frequency dependence can be understood by inclusion of the larger-activation-energy phenomena, such as “a deep acceptor level” and “2DHG confined by fixed charges”. These findings are believed to contribute to building new production platforms of high-performance power semiconductor devices utilizing the polytype heterostructure of SiC.

Abstract: We have investigated the applicability of a new type of 3C-SiC powder source material during PVT growth which consist of a particle size of ca. 10 µm (aggregates up to ca. 150 µm). In-situ X-ray visualization of 75 mm and 100 mm PVT growth runs showed a smooth SiC powder consumption during growth. Using Raman spectroscopy, we have found a high 4H-SiC polytype stability and a low residual stress distribution in the intentionally n-type doped grown crystals.

Abstract: To generate both two-dimensional electron gas (2DEG) and two-dimensional hole gas (2DHG) at will in SiC polytype heterojunctions, simultaneous lateral epitaxy (SLE) method has been extended to form epilayers of alternating stacks of 4H-and 3C-SiC, which includes the first formation of single-domain 4H-SiC on 3C-SiC. The process starts with a spontaneous generation of mononuclear 3C-SiC on the atomically flat wide terrace on 4H-SiC, which expands parallel to the basal plane to form a single-domain 3C-SiC layer having the coherent interface with the underlying 4H-SiC layer. Step-controlled epitaxy is then applied using the adjacent 4H-SiC steps to grow an alternative 4H-SiC layer on top of the 3C-SiC surface, forming another coherent interface. The crystal structure, the interface structure, and the carrier distribution of this stacked epilayers was analyzed. Finally, it is demonstrated that 2DEG occurs at the coherent interface between the 3C-SiC Si-and 4H-SiC C-faces and 2DHG at the 3C-SiC C-and 4H-SiC Si-faces.

Abstract: The memory effect of Al doping in 3C-SiC prevents sharp interfaces between layers of different doping levels and can lead to unintentional doping of subsequent epilayers and even growth runs. Introducing HCl into the growth phase of 3C-SiC reduces the Al incorporation but has a significant impact on Al dopant decay rates and background levels within the chamber, resulting in far sharper doping profiles. The impact of relatively high flow rates of HCl is low within a chlorine-based growth system giving fine control over its influence on the growth process and memory effect.

Abstract: The layer structure of 3C-SiC stacked on 4H-SiC is implemented by simultaneous lateral epitaxy (SLE). The SLE, involving spontaneous nucleation of 3C-SiC(111) on the 4H-SiC(0001) surface followed by step-controlled epitaxy, facilitates the creation of a single-domain 3C-SiC layer with an epitaxial relationship to the underlying 4H-SiC, establishing a coherent (111)//(0001) interface aligned in the basal plane. An extremely low state density at an interface between thermally grown SiO₂ and SLE-grown 3C-SiC layer is revealed by local deep level transient spectroscopy (local-DLTS) based on scanning nonlinear dielectric microscopy (SNDM).

Abstract: In this paper the stress field distribution in 3C-SiC (111) resonators has been studied by micro-Raman measurements and COMSOL simulations. The measurements show that the asymmetry of the anchor points configuration produce an asymmetry in the stress filed distribution. This behavior has been confirmed also by the simulations. Furthermore, from the simulations the importance of the reduction of the under etching of the anchor points of the resonators has also been observed. In fact the reduction of this under etch produces a decrease of the stress in the double clamped beams, a small reduction of the resonance frequency, and a large reduction of the Q-factor and then of the oscillation frequency stability of the resonators in closed-loop operation.

Abstract: In this work, the fabrication of wafer-level vacuum packaged 3C-SiC resonators obtained from layers grown on <100> and <111> silicon is reported. The resonant microstructures are double-clamped beams encapsulated by glass-silicon anodic bonding using titanium-based vacuum gettering. Open-loop resonance frequency measurements are performed on the vacuum-packaged devices showing Q-factor values up to 292,000 for <100> and 331,000 for <111> substrates, with a maximum vacuum level around 10^-2 mbar inside the encapsulations with Ti getter.

Abstract: Free standing wafers of the cubic polytype of silicon carbide (3C-SiC) grown on micromachined silicon substrates can be a platform for new power electronic devices, provided that suitable device fabrication processes are understood and optimized. In this frame, p-type doping is still an open issue, as results on the electrical activation of ion implanted Al in 3C-SiC are limited. This work analyses high level p-type doping with post-implantation annealing carried out at temperatures in the range 1650-1850 °C with different durations. A coherent picture emerges, showing that the resulting resistivity in 3C-SiC Al-implanted layers is higher than the one obtained in 4H-SiC implanted layers, the result being ascribed to low carrier mobility and possibly presence of compensation centers, rather than to poor Al electrical activation. The reported results highlight the importance of working on material and processing optimization.

Abstract: We verify experimentally to what extent the intensity of 3C-SiC TO peak in infrared reflectance spectrum can be used to estimate the thickness of extremely thin 3C-SiC epilayers on Si. The influence of several Si substrate characteristics (orientation, doping level, back-side surface preparation) on the peak calibration is discussed.

Abstract: X-Ray diffraction measurements of lattice parameter were performed for (111) and (100) oriented 3C-SiC/Si epiwafers. Strain of 3C-SiC epilayer and Si substrate were estimated and the result was compared with routine wafer deformation measurements. An unexpected discrepancy was observed between XRD and curvature measurements for (100) oriented samples.