Papers by Keyword: 3C-SiC

Abstract: This study offers a comprehensive examination of the behavior of 3C-SiC crystals grown on 4° off-axis (100) Si substrates with different off-axis angles along <110> and <100> for N and Al doping, respectively. The investigation takes advantage of molten KOH etching to conduct an in-depth investigation of the average density and size of the SFs inside the crystal for both n- and p-type doped 3C-SiC epitaxial layers. Moreover, 3C-SiC grown on a <100> off-cut substrate was revealed to have a greater concentration of SFs due to the absence of self-annihilation along the plane (-1-10). Considering two different doping ranges suitable for IGBTs and MOSFETs development, the impact of doping and off-angle on the crystal quality, concentration, and length distribution of SFs was then investigated in order to quantify the influence of N and Al incorporation on the structural and optical characteristics of the semiconductor. It turned out that under heavy nitrogen doping (~10¹⁹ cm^-3), when the dopant concentration grew, the average length of the stacking faults (SFs) expanded while their density dropped.

Abstract: This paper presents a macro-and nanoscale electrical investigation of Schottky and metal-oxide junctions with hetero-epitaxial 3C-SiC layers grown on Si. Statistical current-density-voltage (J-V) characterization of Pt/3C-SiC Schottky diodes showed an increase of the reverse leakage current with increasing the devices diameters. Furthermore, C-V and J-V analyses of SiO₂/3C-SiC capacitors revealed non-idealities of the thermal oxide, such as a high trapped positive charge (3×10¹² cm⁻²) and a reduced breakdown field (E_BD=6.5 MV/cm) compared to ideal SiO₂. Nanoscale electrical characterizations by conductive atomic force microscopy (CAFM) and scanning capacitance microscopy (SCM) allowed to shed light on the origin of non-ideal behavior of Schottky and thermal oxide junctions, by correlating the morphological features associated to 3C-SiC crystalline defects with local current transport and carrier density.

Abstract: This work investigates the 3C-SiC heteroepitaxial growth on silicon substrates having a wide variety of orientations, i.e. (100) on axis and 2°off, (111), (110), (211), (311), (331), (510), (553) and (995). All the 3C-SiC layers were grown using the same two-step CVD process with a growth rate of 2 μm/h. According to X-ray diffraction characterizations, direct heteroepitaxy (layer having exactly the same orientation as the substrate) was successful on most of the Si substrates except for (110) one which was the only orientation leading to obvious polycrystalline deposit. Each layer led to a specific surface morphology, the smoothest being the ones grown on Si (100)2°off, and (995) substrates. None of these layers cracked upon cooling though those grown on Si (111), (211) and (553) substrates were highly bowed.

Abstract: Analysis of hot-filament CVD (HF-CVD) growth of high quality 3C-SiC on micron-sized 3C-SiC mesas is presented. Two types of growth were observed: 1) a relatively slow growth at about 1μm/hour, and 2) an almost three times faster growth, correlated with the presence of domain boundaries in, or adjacent to, the mesas. Both reveal well-defined crystallographic facets and sharp corners between them. The slower growth has been identified to be surface-nucleation-limited, seemingly defect-free, while the faster growth has been identified as being caused by defect-induced step-flow growth. A growth model is presented, yielding a growth rate of 1.18 μm/h for the defect free {111} and (100) plane and 2.8 μm/h for {110} planes.

Abstract: In this contribution we investigate the formation at high temperature of an oriented 3C-SiC seed on various orientations of Si substrates “pre-carbonized” through Plasma Immersion Ion Implantation (PIII) process.

Abstract: We report the study of the effect of the growth rate and of the doping on the stress and the defect density of a Cubic Silicon Carbide (3C-SiC) bulk layer grown at low temperature on a silicon substrate. After the growth process, the silicon substrate was melt inside the CVD reactor used for the deposition and then the intrinsic stress was measured by the curvature of the wafer without influence of the thermal stress between silicon and 3C-SiC. A considerable increase of the curvature was observed increasing the doping of the layer. The average stress is compressive and then produces a convex bow. At the same time, the average quality of the grown material deteriorates increasing the doping concentration. Using μ-Raman measurement in cross-section of the 3C-SiC grown samples, it was possible to observe the dependence of the stress and of the quality of the material as a function of the thickness and of the growth rate, due to the variation of the growth rate during the process. In particular, the increase of the growth rate produced both an increase of the stress and a decrease of the material quality. Furthermore, the increase of the doping concentration produced both an increase of the stress and a further deterioration of the crystal quality.

Abstract: Free standing 3C-SiC wafers with a dimeter of 50 mm and a thickness of ca. 0.8 mm have been grown on a regular base using 3C-SiC CVD seed transfer from Si wafers to a poly-SiC-carrier and a sublimation epitaxy configuration. Up to the thickness of almost 1 mm, stable growth conditions of the cubic polytype have been achieved. The high supersaturation was kept stable by the proper design of the hot zone that enables a high axial temperature gradient at the growth interface. The Sirich gas phase was realized by the application of a Tantalum getter that was integrated into the graphitebased growth cell. Furthermore, an adaption of the growth setup allowed the growth of 3C material with a diameter of 95 mm and bulk material up to 3 mm on 25 mm diameter. Computer simulations were used to determine the supersaturation of the growth setup for different source-to-seed distances. The minimum supersaturation necessary for stable growth of cubic SiC was found to be higher 0.1 for seed already containing the required 3C polytype.

Abstract: 3C-SiC technology has advanced a lot in the last decade and the interests in making 3C-SiC power devices are growing again, in research and industry. Despite of that, there has been a lack of knowledge on the reliability of the 3C-SiC MOS structure. In this paper, we investigated the MOS capacitors fabricated on 3C-SiC/Si substrates at room temperature. From the simple I-V characterisation, an effective barrier height as high as 3.65-3.71 eV can be extracted for the fabricated 3C-SiC/SiO₂ interface. Reliability test under elevated gate bias which lasts weeks demonstrates an acceptable failure rate (3450 PPM) for these state-of-the-art 3C-SiC MOS capacitors. The failure mechanism study suggests the intrinsic region is still not reached and there is still much room to improve the reliability. Minimising some obvious extrinsic defects which lead to early breakdown alone can reduce the failure rate by 100 times.

Abstract: We have performed density-functional calculations in order to clarify atomic structures and energetics of surface steps on SiC. The obtained energetics of distinct step types on vicinal 3C-SiC(111) surfaces which correspond to 4H- and 6H-SiC(0001) surfaces reveals the atom-scale reason for the experimental observation in the past that the step morphology is straight for the SiC(0001) surfaces inclined toward the 〈1-100〉 direction while it is meandering for the 〈11-20〉 inclined surfaces. The calculations clarify the rebonding between upper- and lower-terrace edge atoms, which is decisive for the energetics of the atomic steps.

Abstract: During the last decade, silicon carbide (SiC) and its heterostructures with other semiconductors have gained a significant importance for wide range of electronics applications. These structures are highly suitable for high frequency and high power applications in extremely high temperature environments. SiC exists in more than 200 different polycrystalline forms, called polytypes. Among these 200 types, the most prominent polytypes with exceptional physical and electrical attributes are 3C-SiC, 4H-SiC and 6H-SiC. Heterostructures of these SiC polytypes with other conventional semiconductors (like Si, Ge) can give rise to interesting electronic characteristics. In this article, Germanium (Ge) has been used to make heterostructures with 3C-SiC and 4H-SiC using a novel technique called diffusion welding. Microscale and nanoscale simulations of nn-heterojunction of Ge/3C-SiC and Ge/4H-SiC have been done. Microscale devices have been simulated with a commercially available semiconductor device simulator tool called Silvaco TCAD. Whereas nanoscale devices have been simulated with QuantumWise Atomistix Toolkit (ATK) software package. Current-voltage (IV) curves of all simulated devices have been calculated and compared. In nanoscale device, the effects of defects on IV-characteristics due to non-ideal bonding (lattice misplacement) at heterojunction interface have been analyzed. Our simulation results reveal that the proposed heterostructure devices with diffusion welding of wafers are theoretically possible. These simulations are the preparations of our near future physical experiments targeted to fabricate SiC based heterostructure devices using diffusion bonding technique.