Papers by Keyword: 4H-SiC

Abstract: Thermal annealing plays a crucial role for healing the defectiveness in the ion implanted regions of DIMOSFETs (Double Implanted MOSFETs) devices. In this work, we have studied the effect of a double step annealing on the body (Al implanted) and the source (P implanted) regions of such devices. We found that a high temperature annealing (1750°C, 1h) followed by a lower temperature one (1500°C, 4h) is mandatory to achieve low defects concentration and good crystal quality in both the n-and p-type zones of the device.

Abstract: In this work, TCAD modeling of a 1200 V SiC MOSFET is presented. The main focus is on modeling of the channel mobility, and the Coulomb scattering by interface traps and surface roughness are therefore included. For the Coulomb scattering, the interface trap profiles have been extrapolated from the subthreshold characteristics at room temperature, whereas the scattering due to surface roughness has been fitted by comparing to the transfer characteristics at high gate bias. A comparison with measurements for the transfer characteristic and the output characteristic is also presented. Results show that the reduction of the threshold voltage with increasing temperature and the temperature dependence of the output characteristics are properly modeled.

Abstract: This paper proposes a novel high-gain 4H-SiC BJT structure with a p-type epitaxial layer on top of the extrinsic base layer. The current gain of the novel structure is improved by 140% compared with the conventional one by the simulator tool with the number of reasonable interface traps, which could be ascribed to the epitaxial layer to reduce the surface recombination in the extrinsic base. The process to fabricate this structure is also proposed in the paper.

Abstract: 4H-SiC pMOSFETs with Al-doped S/D and NbNi silicide ohmic contacts were demonstrated and were characterized at up to a temperature of 200 °C. For the pMOSFETs, silicides on p-type 4H-SiC with Nb/Ni, NbNi alloy, Ni and Nb/Ti were investigated, and the Nb/Ni silicide with the contact resistance of 5.04×10^-3 Ωcm² were applied for the pMOSFETs.

Abstract: A correlation between field effect mobility and an accumulation conductance has been investigated at 4H-SiC MOS interface with barium. 4H-SiC n-channel MOSFETs and n-type MOS capacitors were fabricated with a barium-introduced SiO₂ and a conventional dry SiO₂. The field effect mobility was enhanced by introducing the barium-introduced SiO₂. It is found that there is a linear correlation between the mobility and the accumulation conductance. The MOS interface of the barium-introduced SiO₂ had a lower interface state density of 2×10¹¹ cm^-2eV^-1 than that of the conventional dry SiO₂.

Abstract: The effect of a gate trench bottom p⁺ region (BPR) on the dynamic characteristics of 4H-SiC double-trench MOSFETs was investigated. Although employing a BPR led to an improved trade-off in the static characteristics, a BPR adversely affected the switching characteristics in spite of a reduction in the Miller capacitance compared to the case without a BPR_. Simulation analysis revealed that a resistance between a BPR and a source electrode led to an increase in the switching loss. We have found reduction of the resistance is insufficient in order to provide benefits from the BPR. Hence, it is necessary to improve layouts of contacts of the BPR to the source electrode.

Abstract: We investigated the impact of high-temperature H₂/Ar mixture gas treatment of 4H-SiC(0001) surfaces before SiO₂ deposition on the electrical properties of SiO₂/SiC interfaces. Physical characterizations revealed that the SiC surface treated by the H₂/Ar mixture gas exhibited a (√3×√3)R30° structure composed of Si-O bonds, indicating that a well-ordered and stable silicate adlayer was formed by the treatment to passivate SiC(0001) surface. Electrical defects at the CVD-grown SiO₂/SiC interface was significantly reduced by the treatment. Consequently, a peak electron mobility in SiC-MOSFETs with the deposited gate oxides was enhanced to 24.9 cm²/Vs.

Abstract: For high voltage SiC bipolar devices, carrier lifetime is an important parameter, and for optimization of device performance, we need to control distribution of the carrier lifetime in a wafer. So far, there have been limited systems for depth-resolved carrier lifetime measurements without cross sectional cut. In this study, we adopted a free carrier absorption technique and made local overlapping of the probe laser light with excitation laser light to develop depth-resolved carrier lifetime measurements. We named the developed system a microscopic FCA system and demonstrated measurement results for samples with and without intentional carrier lifetime distribution.

Abstract: To investigate effect of stacking faults (SFs) on switching reliability, we carried out switching tests using SiC-MOSFETs containing expanded SFs. Before the switching test, current stress was applied to the internal body-diode devices under test (DUTs) to expand SFs. The circuit configuration of the switching test we used was a half-bridge type and a double-pulse gate signal was applied to the lower arm DUT. The switching-voltage was 1.8kV and switching-current increased in about 8A steps to breakdown. Reverse recovery safety operation area (RRSOA) breakdown switching-current decreased dependently on the degree of SiC-MOSFET degradation. Reverse bias SOA (RBSOA) did not decrease even if degraded SiC-MOSFETs were used.

Abstract: A box cell layout and a hole-barrier structure were used to realize low-on-voltage n-channel 4H-SiC IGBTs with 6.5-kV blocking capability. Box cell layout can increase the channel width, leading to reduction of the channel resistance and an enhancement of electron injection from an emitter. Hole-barrier structure, which is a potential barrier for holes to prevent them from flowing out of the emitter, can enhance conductivity modulation. An on-voltage of 3.98 V at a collector current of 100 A/cm² was achieved from a fabricated SiC IGBTin this study. Since the on-voltage of a SiC IGBT with a conventional structure was 4.81 V at the same collector current, the effect of our new structure was successfully shown to reduce the on-voltage of SiC IGBTs. An estimation of each voltage component involved in the on-voltage was also carried out by utilizing a device simulation, and the estimation shows that a SiC IGBT incorporating a box layout and hole-barrier structure will thus have quite a low drift-layer voltage and an on-voltage close to the limit determined by the bipolar built-in voltage.