Papers by Keyword: Analog-to-Digital Converter (ADC)

Abstract: This study proposes a Mahalanobis Distance Measurement (MDM) method to analyze current waveform for determining the motor’s quality types. The MDM method consists of three major stages: (i) the preprocessing stage which is for enlarging motor current waveforms’ amplitude and eliminating noises, and includes signal amplitude amplifier, filter circuit (eliminating noises), and analog-to-digital converter (ADC) parts, (ii) the qualitative features stage which is for qualitative feature selection on motor current waveforms, and (iii) the classification stage which is for determining motor quality types using the MDM method. It can recognize defective motors and their defective types in less than 0.5 second. In the experiment, the total classification accuracy (TCA) was approximately 99.03% in average. The proposed method has the advantages of good detection results, no complex mathematic computations, hi-speed, and hi-reliability.

Abstract: A high speed, low offset fully differential comparator for high-speed analog-to-digital converter which can work at a sampling rate of 8GS/s is presented in this paper. The three-stage pre-amplifiers in the improved comparator structure is proposed to ameliorate its gain. The positive feedback regeneration circuit and the improved output buffer are used to ameliorate the comparator bandwidth. Operating with an input sine signal of 1GHz frequency, the circuit can oversample up to 8GS/s with 5bits of resolution. The simulated offset voltage of the comparator by Monte Carlo at 8GHz clock is 5.09mV.

Abstract: This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm². It results in a figure-of-merit (FOM) of 0.11pJ/step.

Abstract: The main challenges of high-resolution ADC testing are the huge number of samples and the expensive test equipment, especially the requirement of high linearity signal source. In this paper, the scaling and segmentation algorithm which combines SEIR with windows is introduced for high-resolution ADC test. The new approach is validated by simulation with a 24-bit sigma-delta ADC. INL error of the proposed method is ±0.2LSB, which is less than the SEIR method of ±0.5LSB,and less than the histogram method of ±0.3LSB. About 20 million samples are required in the proposed method, which is about 30 times less than the traditional histogram method.

Abstract: This paper presents the chip design strategy of resistance type humidity readout circuit for greenhouse application. The designed chip includes resistance change type humidity readout circuit, temperature compensation circuit, low voltage dropout generator (LDO), and analog to digital convertor (ADC).The humidity sensor which used in this research is HCZ_H8, and it is produced by Ghitron Company .Because resistance change type humidity sensor depends much on the temperature, so this paper develops a temperature sensing circuit to compensate the effects caused by the temperature change. The ADC in this research is13-bit fully-differential incremental delta sigma A/D converter, and the power supply is 3.3v, but the power supply of the humidity readout circuit is 5v, so a low voltage dropout generator (LDO) is included to match the power supply.

Abstract: This paper describes boost converter with closed loop discrete Proportional, Integral and Derivative (PID) controller are designed and simulated. The dynamic performance of the boost converter can be improved by the design of discrete PID PWM controller. Discrete PI Controller, Analog PI & PID Controller of boost converter is designed and simulated whose performance parameters are compared with the Discrete PID Controller is illustrated. The DC–DC converter can withstand its regulation performance with the variations in input supply voltage, circuit inductance, capacitance and load resistance.

Abstract: Numerous applications require very precise time measurement. Usually, the measurement accuracy is increased by improve the MCU MIPS. It will take the high cost and current consumption, and the accuracy is limited in the MCU MIPS. Using CTMU channels work in conjunction with Analog to Digital converters, the high precise time measurement with low cost MCU can be achieved, and make the time measurement resolution to 1 nanosecond. CTMU module is available in many Microchip microcontrollers.

Abstract: There are many kinds of ADC chips which are analog or analog-digital mixed at home and abroad. It can not be integrated into a pure digital chip, in this paper, a way to realize quasi-digital 16- bit ADC based on stochastic logic was given. Except few analog elements, all are digital circuits. The paper describes the design principle and presents the simulation and hardware test results based on FPGA chips produced by Altera show that the shortest conversion time can reach 0.8ms. The hardware test shows that the design is successful.

Abstract: This paper presents an advanced analog-to-digital conversion technique based on a voltage-to-frequency-to-digital conversion that is suitable for remote sensors, telemetry applications and multichannel data acquisition systems. A voltage-to-frequency conversion part can be based, for example, on high performance, charge-balance voltage-to-frequency converter (VFC), where monostable is replaced by a bistable, driven by an external clock, or other existing high performance VFCs. The frequency-to-digital converter “bottleneck” problem in such promised ADC scheme was solved due to proposed advanced method of the dependent count for frequency-to-digital conversion. This ADC technique lets receive many advantages such as high accuracy, relatively low power consumption, low cost solution, wide dynamic range, great stability and faster conversion time in comparison with existing VFC-based techniques. The conversion rate (6.25 µs to 6.25 ms) in such ADC scheme is programmable, non-redundant, shorter than for pulse counting technique and comparable with successive-approximation and Σ- ADC.