Papers by Keyword: Atomic Layer Deposition (ALD)

Abstract: In this work, we demonstrate a novel oxidation-free gate oxide process consisting of a two-step surface preparation treatment, followed by atomic layer deposition of SiO₂ and a post-deposition anneal in nitrogen. The surface treatment includes a 1300°C anneal in hydrogen and dilute silane, followed by decoupled plasma nitridation (DPN). Long channel MOSFETs fabricated with this process show a 1.5X improvement in peak field effect mobility compared with devices utilizing a standard thermal oxide and NO anneal. The MOSFETs had a positive threshold voltage, low gate leakage, and a breakdown field of nearly 10 MV/cm.

Abstract: The increased demand for SiC power MOSFETs requires gate dielectrics with low defect densities and high reliability under high electric field and temperature conditions. In this work, we examine how oxidant chemistry and deposition temperature affect the electrical properties of Al₂O₃/SiO₂ bilayer dielectrics formed in n-type 4H-SiC MOS capacitors. These structures consist of a thin SiO₂ interfacial layer, over which Al₂O₃ is deposited via ALD using three different oxidants at a temperature of 150–350°C. C–V and temperature-dependent I–V (25–150°C) measurements show that the choice of oxidant influences the flat band voltage shift and leakage current density, with a process-dependent trade-off between optimizing each parameter. These findings highlight that precise control of oxidant chemistry during ALD is essential for balancing flat band voltage stability with leakage suppression, and that multilayer-specific conduction models are critical for accurately predicting high electric field leakage characteristics in advanced SiC gate stacks.

Abstract: This work investigates the impact of different gate oxide fabrication schemes on the electrical characteristics of 4H-SiC planar MOSFETs. Three processes were implemented: (1) 50 nm thermal oxidation with NO annealing at 1350°C, (2) 50 nm ALD-grown oxide with NO annealing at 1250°C, and (3) a stacked 20 nm thermal/30 nm ALD oxide structure with NO annealing at 1250°C. Electrical characterization included I_dV_g, CV, and I_gE_ox measurements. Results show that Condition 1 exhibits the lowest leakage and best uniformity, and demonstrates strong oxide integrity without soft breakdown events. In contrast, Condition 2 and 3 show increased leakage, higher variability, and evidence of soft breakdown, suggesting greater interfacial weakness. However, a surprising trend was observed in the CV analysis: Condition 2’s flat band voltage (VFB​) is closest to the ideal 0V, indicating a lower fixed charge density than Condition 1 [1], which has the most negative VFB​ (≈ -2V). The hysteresis results further highlight differences, with Condition 3 showing the largest hysteresis window (ΔVth​=0.13V). These findings suggest that while the ALD process coupled with a lower-temperature NO anneal (Condition 2) can effectively reduce fixed charges, it does not fully eliminate interfacial defects responsible for increased leakage and soft breakdown. Our results underscore the complex trade-offs in different fabrication schemes, emphasizing that careful interface engineering beyond conventional NO annealing is required to ensure reliable performance in SiC MOSFETs.

Abstract: This study investigates the electric dipole effect at Al₂O₃/SiO₂ interfaces deposited by Atomic Layer Deposition (ALD) on 4H-silicon carbide (SiC) substrates for threshold voltage (V_T) modulation. By incorporating an ultrathin 3nm Al₂O₃ layer onto ALD-deposited 30nm SiO₂, they created an electric dipole that produces a 0.65±0.15V positive shift in threshold voltage after N₂O post-deposition annealing. The dipole-induced voltage shift was validated through both MOS capacitor measurements and lateral MOSFET characterization. Importantly, the threshold voltage enhancement occurred without degradation in field-effect mobility, demonstrating that the dipole effect does not introduce additional scattering centers. This technique offers an effective approach for threshold voltage tuning in alternative semiconductor devices where thermal SiO₂ growth is not feasible, addressing critical challenges in SiC power electronics that require high threshold voltages (>3V) for reliable operation.

Abstract: This paper presents process integration of atomic layer deposition (ALD) SiO₂ as gate dielectric in the 1.7 kV SiC trench UMOSFET. This integration provides a solution for embedding complementary metal oxide semiconductor (CMOS) circuits into the UMOSFET power device, enabling the realization of smart power management integrated circuit (IC) functions in the future. 4H-SiC power MOSFETs have gained increased attention in medium to high power applications recently due to their wide bandgap, high breakdown electric field, and excellent thermal conductivity. The electric vehicle (EV) is one example of an application where the Tesla Model 3 utilizes SiC 650V VDMOSFETs as driving components in its inverter design. Trench MOSFETs are key to achieving these requirements to further scale down power devices while decreasing the specific on-state resistance (R_on,sp). This is challenging with thermal gate oxide on SiC trench MOSFETs due to the anisotropic thermal oxide growth rate on the sidewalls and the bottom of trench or mesa region. Therefore, we propose a novel fabrication process by integrating ALD SiO₂ gate oxide into trench UMOSFET. The R_on,sp of the fabricated device can be reduced to 2.3mΩ-cm², accompanied by a very low density of interface states (D_it) of approximately 5.36x10¹⁰ eV^-1cm^-2. Another feature of this ALD SiO₂ solution for gate oxide is the monolithic integration of the CMOS circuit with the UMOSFET, enabling the realization of smart power IC management.

Abstract: In this study, ZnO nanowire field-effect transistor (FET) with an aluminium-doped ZnO (AZO) and an aluminium (Al) dual layer source and drain contact are fabricated and temperature dependent characteristics in the range of 200 – 300 K are analyzed through experimental measurements. The effect of temperature on threshold voltage, subthreshold slope, transconductance, and field effect mobility are analysed. The transfer curve exhibits a parallel shift toward a negative gate voltage direction with a negative shift of the threshold voltage, an increase in the subthreshold slope, and a field-effect mobility as the temperature rises. The electrical properties of the transistors demonstrate typical behaviour at various temperatures.

Abstract: Atomic Layer Deposition (ALD) is an enabling technology which provides coating and material features with significant advantages compared to other existing techniques for depositing precise ultra-thin two-dimensional (2D) nanostructures. ALD provides digital thickness control to the atomic level by depositing film one atomic layer at a time, as well as pinhole-free films even across large and complex areas. The technique’s capabilities are presented on the example of ALD-developed ultra-thin 2D tungsten oxide (WO3) over the large area of standard 4” Si substrates. The discussed advantages of ALD enable and endorse the employment of this technique for the development of hetero-nanostructure 2D semiconductors with unique properties.

Abstract: This work reports on the growth and characterization of Al₂O₃ films on 4H-SiC, by Plasma Enhanced-Atomic Layer Deposition (PE-ALD). Different techniques were used to investigate the morphological, structural and electrical features of the Al₂O₃ films, both with and without the presence of a thin SiO₂ layer, thermally grown on the 4H-SiC before ALD. Capacitance-voltage measurements on MOS structures resulted in a higher dielectric constant (ε~8.4) for the Al₂O₃/SiO₂/SiC stack, with respect to that of the Al₂O₃/SiC sample (ε~ 6.7). Moreover, Current density-Electric Field measurements demonstrated a reduction of the leakage current and an improvement of the breakdown behaviour in the presence of the interfacial thermally grown SiO₂. Basing on these preliminary results, possible applications of ALD-Al₂O₃ as gate insulator in 4H-SiC MOSFETs can be envisaged.

Abstract: The influence of thickness of atomic layer deposited Al₂O₃ films on nanotextured fluorescent 6H-SiC passivation is investigated. The passivation effect on the light emission has been characterized by photoluminescence and time-resolved photoluminescence at room temperature. The results show that 20nm thickness of Al₂O₃ layer is favorable to observe a large photoluminescence enhancement (25.9%) and long carrier lifetime (0.86ms). This is a strong indication for an interface hydrogenation that takes place during post-thermal annealing. These result show that an Al₂O₃ layer could serve as passivation in fluorescent SiC based white LEDs applications.

Abstract: Ceramic oxide thin films are an important material, with applications in many areas of science and technology. Titanium oxide (TiO₂) is also a well-known and important material for applications such as gas sensors [1], photocatalysis materials [3], and electrochemicals [1], due to its self-cleaning [2], good corrosion resistance and biocompatibility. Atomic Layer Deposition (ALD) is a nanotechnology tool that is used for the deposition of nanostructured thin films. The unique advantage of ALD is the self-limiting film growth mechanism, which offers attractive properties, simple and accurate film thickness control, sharp interfaces, uniformity over large areas, excellent conformality, good reproducibility, a multilayer processing capability, and high quality films at low temperatures [3, 4]. TiO₂ thin films were grown using TTIP (Titanium isopropoxide) ALD on silicon wafers, glass slides, and stainless steel plates in order to study the effect of substrates on the growth of TiO₂. In order to achieve the desired advantages of using TTIP, a series of experiments were performed to study the growth mechanism of TiO₂ thin films using TTIP and H₂O by ALD.