Papers by Keyword: Avalanche

Abstract: A comparative study of state-of-the-art commercial 1200V trench-gate, planar-gate, and trench-assisted planar Silicon Carbide (SiC) MOSFETs is presented. The experimental study mainly focuses on disclosing the static and robustness characteristics of distinct SiC technologies targeting automotive applications under room and high temperatures. The benchmark study of static characteristics covers specific on-resistance (R_ON,SP), gate leakage (I_GSS​), drain leakage (I_DSS​), breakdown voltage (BV_DSS​), and drain-induced barrier lowering (DIBL) effects. The avalanche robustness is investigated by the unclamping inductive switching (UIS) setup under 25 °C and 175 °C while the single-pulse and repetitive short-circuit capability is evaluated under hard switching fault (HSF) under 25 °C.

Abstract: We are investigating 4H-SiC avalanche photodiodes for use as solar-blind, single-photon UV detectors, which could enable low cost, size, weight, and power devices that are reliable and robust, suitable for many sensing applications. One concern for these devices is the spatially-nonuniform gain which limits the useful device area and impedes the scaling necessary to compete with leading UV sensor architectures. We examined various potential sources of the nonuniformity, and conclude that the typically observed phenomenon is likely caused by impact ionization anisotropy and the 4° wafer offcut angle needed to maintain a consistent polytype during epitaxial growth. Additionally, we present both linear and Geiger-mode spatial maps on the same devices to explain the observed differences in each.

Abstract: Due to the lack of internationally accredited quality standards for silicon carbide (SiC) epiwafers, vendors provide defect maps using different metrology techniques and naming conventions, making it difficult to draw correlations between defect types and unclamped inductive switching (UIS) behavior. This study tested 1700 V rated Junction Barrier Schottky Diodes (JBS) using materials from five 4H-SiC epiwafer suppliers and concluded that, without maps having industry-standardized defect names and showing precise locations, sizes, and shapes, device manufacturers cannot effectively predict UIS yield and reliability.

Abstract: Channel density design guidelines for SiC trench-gate MOSFETs with low switching loss, and high short-circuit and avalanche capabilities were proposed. The cell and grounding region pitches were used as parameters to control the channel density to investigate the parameter dependence of each transient property. The results suggest a clear difference in the dependence of switching loss reduction and short-circuit/avalanche capability increase on these parameters; however, the extents of dependence of specific on-resistance on the controlling parameters were comparable. The reduction in the grounding region pitch contributed to faster charging of the parasitic drain-source capacitance, which was effective in improving transient characteristics, such as dV/dt at turn-off, and saturation current at short-circuit. Furthermore, a reduction in this distance increased the area-flowing avalanche current and hence, an increase in the avalanche energy. The influence of the two design parameters in effectively improving the trade-off between each transient characteristic and the specific on-resistance was summarized.

Abstract: The effect of the termination structure on the unclamped inductive switching (UIS) failure is analyzed for two kinds of SiC MOSFET, where S-MOS and G-MOS termination structure are adopted. The MOSFETs are named as S-MOS and G-MOS according to the buses connecting with different electrodes in the termination region. The experimental results indicate that the avalanche energy G-MOS can withstand is 1.15 times larger than that of S-MOS. To understand what are the factors that lead to different UIS capabilities, further static measurements and hotpot mapping after UIS test are done, and technology computer aided design (TCAD) simulation also is done to further confirm the principle.

Abstract: This paper presents the comparative study on the repetitive unclamped inductive load switching capabilites in comercialized 1200V, 160mΩ rated SiC MOSFETs. Recently released Littelfuse-Monolith 1200V 160 mOhm design (LSIC1MO120E0160) manufactured through 150mm high volume CMOS compatible process demonstrated excellent R-UIS capabilities: no parametric shift on key electrical performances such as on-resistance, threshold voltage, breakdown voltage and drain leakage current after 100000 cycles of R-UIS stress. Both Competitor A and B design with planar gate showed R-UIS capabilities. All critical parameters were within the datasheet specification after R-UIS test. Competitor A design was equivalent to LSIC1MO120E0160. Competitor B design showed the drain leakage increase after 2000 cycle of R-UIS stress. Competitor C design with trench gate did not exhibit any R-UIS capabilities.

Abstract: The paper is devoted to engineering-hydrometeorological research at the mountain resort Arkhyz. The parameters of avalanches on the territory of the resort, potentially dangerous for objects under construction, are determined. Three avalanches focuses were identified with volumes of removals from 230 to 700 thousand cubic meters of snow.

Abstract: Integrated assessment of snow avalanches, glacial mudflows, outburst floods and rock avalanches to facilities located on the territory of Recreation centre "Polyana Cheget", based on geomorphological analysis, interpretation of multi-temporal aerial and satellite images as well as route surveys has been presented in the article.

Abstract: This paper presents the performance, reliability and ruggedness characterization of 1200V, 80mΩ rated SiC planar gate MOSFETs, fabricated in a high volume, 150mm silicon CMOS foundry. The devices showed a specific on-resistance of 5.1 mΩ.cm² at room temperature, increasing to 7.5 mΩ.cm² at 175 °C. Total switching losses were less than 300μJ (V_DD = 800V, I_D = 20A). The devices showed excellent gate oxide reliability with V_TH shifts under 0.2V for extended HTGB stress testing at 175 °C for up to 5500 hours (V_GS = 25V) and 2500 hours (V_GS = -10V). Ruggedness performance such as unclamped inductive load switching and short circuit capability are also discussed.

Abstract: When power MOSFETs experience a voltage spike initiating avalanche generation, a large amount of power is dissipated at the device junction. This leads to self-heating and lowers the threshold voltage. Some sources indicate that unintended opening of the channel creates a positive feedback, thereby increasing heat generation and leading to thermal runaway. Therefore, keeping MOSFETs off by applying a negative gate bias should improve avalanche ruggedness. In this report, this claim is investigated by comparing single pulse avalanche ruggedness of commercial 1.2 kV, 80 mΩ planar and trench MOSFETs at -10 V and 0 V off-state gate bias. Both planar and trench devices show a small increase in their breakdown voltage with negative gate bias. However, there is no significant difference in avalanche withstanding energy. Even in investigated trench gate devices where the gate oxide is susceptible to interface as well as oxide defects, keeping the gate voltage at V_GS = -10 V did not result in improvements in ruggedness.