Papers by Keyword: Basal Plane Dislocation (BPD)

Abstract: Silicon carbide (SiC) wafers are essential for next-generation power devices, however conventional dicing methods often induce cracks and Basal Plane Dislocations (BPDs), reducing device reliability. This study demonstrates BPD-free dicing of epitaxial SiC wafers using Water jet Guided Laser (WGL) processing. Full-thickness cutting was performed on 350 μm-thickness wafers with a 10 μm-thickness epitaxial layer using a YAG laser (532 nm wavelength, 200 ns pulse width, 10 kHz repetition rate, 30–80 W output) on an LB300 system. BPD evaluation was carried out by X-ray topography (XRT) with the-1-128 reflection before and after cutting. The results showed no generation or propagation of new BPDs, and pre-existing BPDs did not glide, confirming that WGL processing enables BPD-free machining. These results are attributed to the ablation-based nature of WGL with water assistance, which avoids mechanical stress on epitaxial SiC wafers.

Abstract: Silicon Carbide (SiC) is a pivotal wide-bandgap semiconductor for high-power and high-frequency electronics. However, crystalline defects, particularly Basal Plane Dislocations (BPDs), severely degrade the performance and reliability of bipolar devices by nucleating stacking faults that cause fatal forward voltage drift. This work presents the successful growth of 8-inch, 4° off-axis, n-type 4H-SiC single crystals with significantly reduced BPD density via the Physical Vapor Transport (PVT) method using an improved reactor design. The key innovation involves replacing traditional graphite components with single or polycrystalline SiC for the seed holder and guide tube, subsequently coated with a thin (10 µm) tantalum carbide (TaC) film. This design ensures thermal expansion coefficient matching and reduces thermal radiation emissivity. Etch pit density analysis revealed that the improved design reduced the overall BPD density from over 1027 cm⁻² to a remarkably low 78 cm⁻². Furthermore, it drastically improved the radial uniformity of BPD distribution by stabilizing the thermal gradient and suppressing parasitic polycrystalline nucleation, marking a critical advancement towards high-yield production of high-quality, large-diameter SiC substrates.

Abstract: This work explores the role of implantation depth in suppressing bipolar degradation of 4H-SiC PiN diodes through proton implantation. Targeting depths aligned with active basal plane dislocations (BPDs) effectively reduces stacking-fault expansion, as confirmed by electroluminescence imaging [1,2]. From these observations, we quantified the effective range of suppression in both depth and safe operating current density. Room-temperature proton implantation (170keV, 1×10¹⁶ cm^-2) into the buffer reduced forward-voltage drift ΔV_F by 97% at 600A/cm². The implanted diode extended the safe operating current range to 1300A/cm², ~200A/cm² higher than the reference, confirming effective suppression of bipolar degradation. Once the suppression barrier, defined as a critical excess hole density threshold, was exceeded, the proton-implanted diode exhibited explosive basal plane dislocation activity, leading to the formation of multiple bar-shaped stacking faults. These active BPDs are located deeper than the proton-implant tail, at a depth of around 11.4µm; however, the threshold hole density required for their activation remains approximately the same (~ 4×10¹⁶ cm^-3) [3].

Abstract: Suppressing the expansion of Single Shockley-type stacking faults (1SSFs) is critical for the growing demand of high-performance power devices. However, the underlying suppression mechanism has not yet been fully elucidated. Through proton ion implantation studies, we have established a fundamental approach by modeling this phenomenon. Carbon vacancy (V_c) generated by high-energy proton implantation are found to play a significant role in suppressing the expansion of 1SSFs.

Abstract: Basal plane dislocations (BPDs) represent one of the most detrimental defects in 4H-SiC epitaxial wafers, causing forward voltage degradation in bipolar and power FET devices through the formation and expansion of Shockley-type stacking faults (SSFs). This expansion is driven by the recombination-enhanced dislocation glide (REDG) mechanism during forward bias operation. Despite efforts to mitigate BPD effects by converting them into threading edge dislocations (TEDs) via buffer layer engineering, throughout the epitaxial growth SSFs can still nucleate and propagate, particularly under high current injection. This work presents a comprehensive analysis combining electrical characterization, fault localization technique, Scanning Electron Microscopy (SEM) and micro-photoluminescence (μ-PL) to investigate SSF formation, crystallographic features, and their impact on device performance. The results underscore the critical role of advanced diagnostics and epitaxial process optimization in controlling SSF-related degradation and improving the reliability of SiC power devices.

Abstract: Ultraviolet (UV) irradiation on 4H-SiC epitaxial wafers, conducted prior to metalized circuit formation, is widely used to reveal whether BPD (basal plane dislocation) induced nucleation and expansion of a single Shockley stacking fault (1SSF) occurs or not via recombination enhanced dislocation glide (REDG). However, the UV method has remained largely qualitative, and its quantitative relationship to forward bias current injection has not been established. Here, using the excess minority carrier density at the BPD-to-TED (threading edge dislocation) conversion point, we establish equivalence criteria between two stress modes (current density and UV irradiance) and introduce a previously overlooked requirement for pulsed UV laser sources: the minority carrier density must exceed a threshold and be sustained for a finite “critical duration,” t_crit. Notably, t_crit shows only weak dependence on the bulk carrier lifetime (τ_b), offering a practical route to determine pulsed UV irradiation conditions that faithfully emulate forward bias stress, even when τ_b is unknown.

Abstract: We have been developing the expansion–visualization–contraction (EVC) method as an inspection technique for 4H-SiC wafers, in which Shockley-type stacking faults (SSFs) are intentionally expanded by UV irradiation and subsequently visualized to identify converted dislocations that are not directly detectable by conventional PL inspection. In this study, we demonstrate a low-cost “operando” PL spectrum mapping approach for the EVC tool by using the 355-nm expansion laser as the PL excitation source and adding only a miniature spectrometer via an optical fiber, avoiding the need for an expensive hyperspectral camera.Two experiments were performed. In Experiment 1, proton-implanted and non-implanted regions on n-type 4H-SiC epilayers were compared using EVC screening and PL imaging. The proton-implanted regions exhibited narrower SSF widths, and a two-sample t-test yielded extremely small p-values, indicating a statistically significant suppression effect that remained after activation annealing. In Experiment 2, a thick epilayer wafer containing polytype inclusions was screened. PL spectrum mapping identified not only 1SSF-related emission (~420 nm) but also Frank-type components (~488 nm) and polytype-inclusion-related emission (~540 nm), revealing composite stacking faults expanded from inclusions. The results suggest that operando PL spectrum mapping can help distinguish stacking-fault types during EVC screening and potentially prevent unnecessary expansion of thermally uncontractable faults, thereby reducing yield loss.

Abstract: This study investigates the role of in-grown stacking faults (SF) in the bipolar degradation of 3.3 kV SiC-MOSFETs, emphasizing their significant contribution to both on-resistance (V_DSon) and leakage current (I_DSX) degradation. A high current stress was applied to over 1,500 chips, resulting in 72 degraded devices, with 45 exhibiting notable I_DSX degradation. A detailed analysis revealed that most I_DSX degraded chips contained bar-shaped in-grown SFs, suggesting a correlation between these defects and leakage current degradation. These findings indicate that peculiar basal plane dislocations associated with in-grown SFs may be critical contributors to I_DSX degradation, indicating the need for further research to elucidate the mechanisms behind this degradation in SiC-MOSFETs.

Abstract: Commercially available 4H-SiC substrate quality has improved over time, and this has extensively reduced defect concentration in the active epitaxial layer, during epi growth conditions at the interface. The objective of this work is to investigate bulk crystal quality for the purpose of future vertical power device fabrication in exfoliated, non-epitaxial, undoped material layers. Mathematical estimations on the device yield fraction, that is immune to bipolar degradation for the suggested future process were calculated based on XRT measurements to detect BPD and TSD densities on donor substrates. The full wafer BPD density maps of on-axis semi-insulating wafer substrates from two vendors were compared.

Abstract: It is known that basal plane dislocations (BPDs) and in-grown stacking faults (IGSFs) in the 4H-SiC epitaxial layer cause severe electrical degradation in SiC devices. The impact that sub-surface damage (SSD) on a production-grade 4H-SiC substrate with CMP-finished surface causes on both the BPD propagation and IGSF formation during epitaxial growth was investigated by Dynamic AGE-ing^🄬 (DA). The substrates etched by DA sublimation etching to adjust the residual amount of SSD maintaining a smooth surface without macro step bunching were grown to observe BPD and IGSF density. The obtained results showed that these defect densities decreased exponentially with increasing etching depth. We demonstrated SSD introduced by mechanical processing led BPDs and IGSFs to extend or introduce to the epitaxial layer.