Papers by Keyword: Basal Plane Dislocation (BPD)

Abstract: We are currently developing an inspection system that will provide a low-cost means of screening prior to shipment by fully visualizing latent 1SSF (single Shockley stacking fault) defects originating from basal plane dislocations (BPDs) that cannot be detected by current defect inspection systems. The system will capture not only the defects that expand into right triangles under relatively low-level forward bias, but also the defects that expand into more serious bar-shaped 1SSFs under relatively high-level forward bias, with a particular focus on capturing TED (threading edge dislocation)-converted BPD at or below the buffer layer/substrate interface. Since these defects are known to cause forward voltage degradation during device operation, so-called "burn-in" (accelerated current stress) screening operation is currently utilized in some device manufacturers to avoid the shipping of the defective devices, but it is very time-consuming process which raises a total cost of production. The system we are developing, which can significantly reduce the screening time, has the potential to replace the "burn-in" operation.

Abstract: In the previous report [1], we proposed the S-EVC (Selective Expansion-Visualization-Contraction) method (Fig. 1) that effectively screens for malignant BPDs (basal plane dislocations) in the drift and buffer layers, which expand to SSFs (Shockley-type stacking faults), leading to forward voltage degradation. The method intentionally utilizes the REDG (recombination enhanced dislocation glide) mechanism by UV (ultraviolet) irradiation in wafer sorting to replace the so-called burn-in (accelerated current stress) process, which is time-consuming during mass production. In the report, triangular SSFs were examined to verify the effectiveness of the method, but they only occupy a much smaller area of the active region on the chip than bar shaped SSFs. In this study, to improve the S-EVC method to be more practical, we focused on the more serious bar shaped SSFs which have a non-negligible impact on electrical characteristics. The bar shaped SSFs are mostly expanded from TED (threading edge dislocation)-converted BPD at or below the substrate epitaxial layer interface. In PL (photoluminescence) observation by a 710 nm LPF (long-pass filter), the TED-converted BPD and the complete TED extended from the bottom of the substrate are observed as the same dark spot, but it was confirmed that both can be distinguished by the presence or absence of their SSF expansion by UV irradiation. In addition, in order to confirm the validity of the S-EVC method even on the virgin epi wafer, UV irradiation was performed on both the aluminum doped PN structured wafer and the virgin epi wafer, and the similar SSF expansion was observed. Meanwhile, the correlation between UV irradiation and forward voltage degradation was quantified using PiN diodes by comparing the glide velocity of 30°Si (g) core partials for bar shaped SSFs by UV irradiation stress with that by current stress.

Abstract: Improving the visibility of defects in nitrogen-doped 4H-SiC (0001) bare wafers by photoluminescence imaging (PLI) is essential for improving the epitaxial growth process and device yields. This study proposes sub-surface damage (SSD) introduced during the mechanical process of SiC wafers as a new factor in reducing defect visibility in PL images. To verify the effect of SSD, we observed the surface of a SiC wafer, which was thermally etched at about 3 μm. As a result, dramatic defect visibility improvement was observed when the surface roughness was sufficiently flat (Ra < 0.3 nm) after thermal etching. Thus, the results suggest that defect visibility in PL images can be improved by controlling SSD and surface roughness. Using the background noise reduction effect of the SSD removal, not only PLI but also many other wafer surface inspections are expected to be improved.

Abstract: To prevent arrays of basal plane dislocations (BPD) forming during grown 4H-SiC single crystals, the growth cell in physical vapor transport (PVT) growth was modified by adapting the temperature gradients, the seed attachment method and the seeding phase. The resulting reduction in stress was modeled numerically and the crystals were investigated by X-ray topography (XRT) and molten potassium hydroxide (KOH) etching. Due to these modifications, the formation of BPD arrays was completely suppressed.

Abstract: In this work, body diode stress has been carried out for 1700 V 25 mΩ planar SiC MOSFETs. The epitaxial wafers were mapped with Infra-Red photoluminescence (IR-PL) to determine and localize the exact number of basal plane dislocations present in the drift layers of each die. The SiC MOSFETs were then packaged in groups with individual BPD counts in different bins ranging from 0 up to more than 30 per device. Pulsed body diode measurements with high currents of 250-400 A (about 1000-1600 A/cm²) were then performed with electrical characterization before and after to check for drift in key electrical parameters. Significantly increased R_DSon was found after high current stress from about 300 A for devices with BPDs. A physical analysis of the degraded devices by backside electroluminescence show the presence of several trapezoid-shaped patterns indicating the occurrence of bipolar degradation.

Abstract: In an increasingly electrified technology driven world, power electronics is central to the entire clean energy manufacturing economy. Silicon (Si) power devices have dominated power electronics due to their low cost volume production, excellent starting material quality, ease of fabrication, and proven reliability. Although Si power devices continue to improve, they are approaching their operational limits primarily due to their relatively low bandgap, critical electric field, and thermal conductivity that result in high conduction and switching losses, and poor high temperature performance. Silicon Carbide’s (SiC) compelling efficiency and system benefits have led to significant development efforts over the last two decades and today planar and trench MOSFETs, and JFETs are commercially available from several vendors as discrete components or in high power modules in the of 650 V to 1700 V voltage range. High impact application opportunities, where SiC devices are displacing their incumbent Si counterparts, have emerged and include automotive and rail power electronics with reduced losses and reduced cooling requirements; novel data center topologies with reduced cooling loads and higher efficiencies; variable frequency drives for efficient high power electric motors at reduced overall system cost; more efficient, flexible, and reliable grid applications with reduced system footprint; and “more electric aerospace” with weight, volume, and cooling system reductions contributing to energy savings. In particular, SiC insertion in electric vehicles brings major competitive advantages and is a volume application opportunity that can spur manufacturing economies of scale and lower system costs. As SiC continues to grow, the industry is lifting the last barriers to mass commercialization that include higher than Si device cost, relative lack of wafer planarity, the presence of basal plane dislocations, reliability and ruggedness concerns, and the need for a workforce skilled in SiC power technology to keep up with the rising demand. It should be noted that in many applications, insertion of SiC reduces overall system cost compared to Si even though SiC devices can cost 2-3 more than their Si counterparts. This is due to the passive component and cooling system simplifications enabled by the efficient high frequency SiC operation. In this paper, we will review key aspects of SiC technology and discuss overcoming barriers to mass commercialization.

Abstract: It is known that generation of interfacial dislocation on SiC epitaxy depends mainly on misfit strain between substrate and the epilayer. In this paper, we investigate the impact of temperature profile, doping profile of the epilayer and resistivity of the substrates on the formation of interfacial dislocation in epilayers. Our preliminary results show that thermal profile during the epitaxy plays a key role in formation of interfacial dislocations in epilayers. We demonstrated reduction or elimination of interfacial dislocation in epilayers by optimizing the temperature profile of the wafers during the epitaxial growth.

Abstract: We propose the new practical and effective method, called Selective E-V-C (Expansion-Visualization-Contraction) technique, to screen out the basal plane dislocations (BPDs) which might cause the forward voltage degradation of SiC devices. Since the method can be adopted at the epi wafer receiving inspection process in early stage of production line, it may replace the very time-consuming so-called "burn-in" operation currently utilized in some device manufacturers.

Abstract: We investigate electrical characteristics of the pn-diode fabricated using the epitaxial films on the surface damage-free 4H-SiC (0001) Si-face 4° off-cut wafers prepared by the completely thermal-chemical etching process; Si-vapor etching (Si-VE) technology. The forward and reverse current-voltage (I-V) characteristics of pn-diodes correlated to the epitaxial defects are discussed. The device at the defect-free area includes 11 % failed diodes on the chemo-mechanical polishing (CMP) wafer while 0 % on the Si-VE wafer. The latent scratches and mechanical damages, which increase the forward and reverse leakage current of the pn-diodes, are completely removed by the Si-VE. The Si-VE exposes the carbon inclusions in the wafer to form the small bump which ends up with the larger bump defect on the epitaxial surface. These bumps cause leak current of the forward characteristics while all of the reverse characteristics are normal. The epitaxial film on the Si-VE surface has less density of the basal plane dislocations (BPDs) than the conventional CMP. It is hard to recognize the safe device on the CMP wafer without additional reliability test. The Si-VE wafer shows the apparent breakdown voltage fail on every small-number diode including BPDs under the simple test. It is considered that the Si-VE is possible to reduce ambiguity of the device characteristics under the relationship with the defects in comparison with the CMP.

Abstract: The expansion behavior of basal plane dislocations (BPDs) in a 4H-SiC epitaxial layer on the (110) A-plane under electron beam (EB) (//[110]) irradiation was observed. BPD expanded and formed a single Shockley stacking fault (SSSF) between a partial dislocation (PD) pair. The width of the SSSF was proportional to the EB current. The dependence of the expansion velocity on the irradiation position was observed with a fixed EB spot. It was found that the electron-hole pair migration to the PD and/or SSSF can expand the SSSF. The velocity of SSSF expansion by direct SSSF excitation with an EB was much smaller than that by the preferential excitation of a PD with migrated electron-hole pairs.