Papers by Keyword: Breakdown Voltage

Abstract: Large-area, 7.84 mm² SiC DMOSFETs feature breakdown voltages of 4600 V, specific on-resistance of 17 mΩ-cm² and gate threshold voltage of 2.4 V. The low on-resistance was enabled by an optimized MOS process that resulted in channel mobility as high as 27 cm²/Vs, and oxide breakdown fields in the 10-11 MV/cm range. The key device design and layout parameters were varied to examine the performance versus reliability trade-offs.

Abstract: Aluminium oxide was deposited on silicon, silicon carbide and epitaxial graphene grown on silicon carbide by atomic layer deposition using a standard MOCVD equipment. The morphology and the electrical properties of the aluminium oxide layers on both substrates were determined and compared to aluminium oxide layers deposited with a standard atomic layer deposition equipment. The high-k material fabricated with the developed MOCVD process show comparable or better properties compared to the standard atomic layer deposition process.

Abstract: Oil impregnated insulation paper plays an important role in a transformer as it insulates the windings from high voltage and current. Other than the type of paper used, the properties of oil such as viscosity, relative permittivity and dielectric loss play a major factor that contributes to the quality of the insulation paper. This paper discussed the sonication and esterification process on palm oil and treated waste vegetable oil and its’ effects on the performance of oil impregnated paper. Basically through these processes, viscosity of oils will reduce. However, the resultant permittivity and dielectric loss as well as its’ breakdown strength are rarely reported. Experiments were set to process (sonicates and esterify) the natural oils prior to the paper impregnation process. Results show that esterification is more effective than sonication process in reducing insulation oil viscosity, relative permittivity and dissipation factors as well as increasing the breakdown voltage of the oil impregnated paper. Palm oil methyl ester (POME) could serve as an excellent insulation oil which is very suitable as transformer oil as well as the impregnation medium for paper insulation.

Abstract: High channel mobility 4H-SiC MOSFETs have been demonstrated by phosphorus and arsenic implantation prior to thermal oxidation in N₂O. The maximum field-effect mobility of 81 and 114 cm²/Vs were achieved, respectively. The MOSFET fabrication was done on lightly aluminium doped p-type epitaxial layers and on heavily aluminium implanted p-well.

Abstract: The leakage currents of high nominal voltage conductive polymer tantalum (Ta) electrolytic capacitors are the difficulties in the research and development processing. The optimized and improved forming technical of increasing current density with the voltage rising was used in the present paper, and silane coupling agent has been used to the dielectric surface of the electrode body before polymerization, and conductive slurry was used to forming the cathode electrolyte of capacitors. Low leakage currents and high breakdown voltage have been tested; otherwise, the endurance capabilities of reverse voltage have prodigious enhanced.

Abstract: Vertical Schottky diodes have been fabricated on low C content Si_1-xC_x and 3C-SiC epilayers epitaxially grown on Si(001) substrates. Significant leakage current was observed in 3C-SiC diodes under reverse bias, masking any rectifying behavior. This issue is far less pronounced in Si_1-xC_x based Schottky diodes which demonstrate a clear critical breakdown. Leakage current is shown to be greater in relaxed Si_1-xC_x layers. While crystalline Si_1-xC_x is not currently a viable material for high power electronics it is useful for assessing the impact lattice mismatch and crystalline quality has on the behavior of rectifiers.

Abstract: A novel method for analyzing a decrease in breakdown voltage (V_BD) in the termination of 4H-SiC power devices after reverse-bias stressing on the basis of change in depletion-layer capacitance is proposed. Test PN diodes terminated with a junction-termination extension (JTE) were fabricated on n-type 4H-SiC and analyzed by I-V and C-V measurements. According to the results of the measurements, V_BD after stressing decreases, and the capacitance of the test devices decreases after stressing. Measurements with different chip sizes but the same termination width show that the capacitance decrease occurs in the termination area. The simulated capacitance change, on the supposition that positive charge accumulated at the SiO₂/SiC interface, and the measured capacitance change show the same tendency. These results indicate that the origin of V_BD decrease is positive charge accumulated at the SiO₂/SiC interface of the termination after reverse-bias stressing.

Abstract: The influences of positive fixed oxide charges and donor-like interface traps on breakdown voltages of SiC devices with FGR and JTE terminations were studied. The breakdown voltages of devices with both FGR and JTE terminations were found to degrade when the level of fixed oxide charges overs 1×10¹² cm^-2 due to enhancement of junction curvature by fixed oxide charges. The introduction of donor-like interface traps at the interface shows similar behaviors as fixed positive charges, suggested that both fixed oxide charges and interface traps should be taken into account when one optimizes device designs and processes.

Abstract: SiC Junction Transistors (SJTs) with 1900 V Drain-Source breakdown voltages, current gain (h_FE) higher than 120 and low on-resistance of 22 mΩ (3.5 mΩ-cm²) are reported in this paper. SJTs with a pre-stress h_FE of 90 suffer only a 10% reduction of the h_FE after 190 hours under a 200 A/cm² DC current stress at a T_J of 125°C, while a similar stress on earlier generation SJTs resulted in over 25% h_FE reduction in only 25 hours. SJT die with pre-stress h_FE in the range of 120-125 show absolutely no current gain degradation even after a 300°C/ 2 hour stress at 60 A/cm² DC drain current.

Abstract: The effect of the alternative nitridation process of the 4H-SiC/SiO₂ interface by introduction of a thin silicon nitride layer on the electrical properties of the gate oxide has been investigated. C-V and G-V measurements on inversion-channel MOS devices revealed similar results to the conventional N₂O oxidation. Higher field-effect mobility values are achieved due to lower interface roughness of the alternative nitridation process. However, insignificant degradation of the reliability was observed.