Papers by Keyword: C-V

Abstract: SiC power MOSFETs show very promising electrical performance for efficient and reliable high temperature operation. This work presents a novel approach for the determination of the temperature dependence of SiC power MOSFET’s channel and drift resistance components in the on-state, which are extracted based on current-voltage (I-V) and capacitance-voltage (C-V) measurements without the need of data extrapolation. The results show that the channel resistance has weak, whereas the drift resistance has strong temperature dependence.

Abstract: Wide bandgap semiconductor technology has been generating a great deal of attention due to its fundamental advantages in high power electronics. Understanding and effective control of interfacial properties belong to a group of critical issues requiring progress. In this work, we report progress in wide bandgap interface characterization, achieved using photo-ionization of deep traps under a non-equilibrium condition created by corona-charge bias in deep depletion. This characterization capability is demonstrated on oxidized n-type epitaxial SiC with deep interfacial traps invisible in standard C-V. These traps, initially present at high density, are shown to be reduced by half after a wet anneal. The photo-ionization technique is incorporated in commercially available non-contact C-V (CnCV) metrology [1,2] providing a non-invasive, cost and time saving metrology that benefits development research as well as device fabrication.

Abstract: We report significant advancements in corona-based non-contact capacitance-voltage (CnCV) metrology recently developed for comprehensive C-V characterization of SiC and other wide bandgap semiconductors. The technique answers the industries needs for nondestructive, cost-effective C-V dopant monitoring for material and device development and manufacturing control. Excellent precision and matching to mercury probe CV is demonstrated for SiC, Ga₂O₃, GaN and AlGaN/GaN structures over a concentration range from 10¹⁴cm^-3 to 2x10¹⁹cm^-3. The emphasis in the present work is on improvement of CnCV in dopant depth profiling resolution and measurement throughout. This is achieved with a variable charge method that in-situ adjusts corona charging increments in response to changes in dopant concentration. Results are presented for multi-layer epitaxial SiC and for 2DEG in AlGaN/GaN HEMT structures. The latter represents an extreme case of high-low concentration profiling with a transition from 10²⁰electrons/cm^-3 in the 2D electron gas to a fully depleted well and dopant concentration in the 10¹⁵cm^-3 range.

Abstract: Schottky barrier height (SBH) has been characterized on 4H-SiC Schottky diodes with metal contact of Ti/W by Current-Voltage (I-V) and Capacitance-Voltage (C-V) measurements between 80 K and 400 K. Multi-barrier has been recognized and calculated according to different models. No clear difference has been found between single barrier diode and diode with multi-barrier from DLTS tests. Evolution on the I-V characteristics has been observed after high temperature annealing. The effect of annealing at room temperature (RT) and high temperature DLTS scan (stress under high temperature) have also been studied on both static characteristics and DLTS results.

Abstract: A simple and practical method of characterizing traps at SiC/SiO₂ interfaces close to the bottom of the conduction band by using the split C−V and Hall measurements is proposed. This technique was applied to the characterization of traps at a wet-oxidized SiC/SiO₂ interface on C-face and those at an oxynitrided SiC/SiO₂ interface on Si-face. It was shown that the density of traps near the conduction band of the oxynitrided SiC/SiO₂ interface was more than 10 times larger than that of the wet-oxidized SiC/SiO₂ interface.

Abstract: A systematic study on the 3C-SiC/SiO₂ interface has been done. 3C-SiC epilayers have been grown on a Si (001) substrate. Results obtained from room temperature conductance-voltage (G-V) and hi-low capacitance-voltage (C-V) on n-type 3C-SiC/SiO₂ metal-oxide-semiconductor capacitors (MOS-Cs) have been reported using various types of oxides. The oxides used in these studies have been thermally grown at different oxidation temperatures - 1200°C, 1300°C and 1400°C. Also, the interface trap density (D_it) of as-grown MOS-C is compared with nitrided (thermally grown oxide + N₂O post-oxidation annealing) oxides. Oxide grown at 1300°C followed by N₂O-passivation at the same temperature gives the lowest D_it of 6x10¹¹ cm^-2eV^-1 at 0.2eV from the conduction band (CB) edge.

Abstract: The effect of annealing temperature on the properties of c-Si wafer/SiO_x interface (x = 1.15 and 1.3) is studied by Transmission Electron Microscopy and Capacitance/Conductance-Voltage measurements. Furnace annealing for 60 min at 700 and 1000 °C is used to grow amorphous or crystalline Si nanoparticles. The high temperature process leads to an epitaxial overgrowth of the Si wafer and an increase of the interface roughness, 3-4 monolayers at 700 °C and 4-5 monolayers at 1000 °C. The increased surface roughness is in correlation with the higher density of electrically active interface states.

Abstract: Metal-Oxide-Semiconductor structures with semitransparent Au top electrode and containing Si nanocrystals in the gate dielectric are fabricated and studied. The structures can be charged negatively or positively by injecting or extracting electrons from the top electrode. Illumination with 395-400 nm, 10.4 mW UV light source causes discharge of previously charged structures with rate which varies between 2 mV/s and 12 mV/s. The discharge rate depends on the sign of the trapped charge, as well on the internal electric field in the gate dielectric.

Abstract: Clay consists of about 50% SiO₂ + 25% Al₂O₃ plus some other oxides with low abundance ratio like CaO, TiO₂, Fe₂O₃, MgO and Mn₂O₃. Burning the clay at 700°C removes out the organic compounds and the mentioned oxides only remain. Our aim is to dope ZnO by the remaining oxides for varistors fabrication. Six types of clay were collected from Egyptian Red Sea Coast mines, after burning for 2 hrs the remaining oxides were mixed and ball milled with ZnO for 10 hrs according to the formula (100-Xn) ZnO +Xn, where n is the clay type and X is the ratio of the clay in grams, X takes the values 0.525 in 15 steps. Samples were pressed and sintered at three different temperatures (T_sin) 1200°C, 1300°C and 1400°C for 1 hr, and then studied via XRD, SEM, EDAX, J-E and C-V measurements. The obtained results were discussed in terms of the microstructure of the samples and the formation of Schottky barriers. Barrier height Ф, width W, interface state density N_s and donor state density N_d were calculated for the samples with highest nonlinearity α. It was found that the breakdown electric field E_o is related exponentially with the ratio of Zinc silicate phase whereas α scales with ratio of ZnO phase and the later increases linearly with T_sin. The electrical characteristics of the most promising sample were compared with those of ZnO samples doped pure SiO₂ and Al₂O₃ obtained at the same preparation condition. This sample is comparable with the Japanese commercial varistor 5N220k Dc JVR.

Abstract: In this paper different characteristic parameters using high-k dielectric materials in Metal Oxide Semiconductor (MOS) device have been compared from the theoretical and simulated Capacitance-Voltage (C-V) graphs. The simulation has been done using ATLAS device simulator. The agreement of the specified values while deriving and simulating and that extracted is excellent. Further, the extracted parameters for high-k dielectric materials show an inferior interfacial quality.