Papers by Keyword: CMOS

Abstract: Precise control of optical transitions of color centers like silicon vacancies (V_Si) in 4H-SiC is essential for their functionalization. An applied electric field (E || c) of a pin-diode can be used to tune the optical properties of V_Si centers via the Stark effect, while the associated space charge region under bias suppresses spectral diffusion. Unlike commonly used 4H-SiC c-plane wafers, a-plane wafers allow a scalable fabrication of lateral pin-diodes and resonant laser excitation of the V_Si perpendicular to the wafer surface (a ⊥ c). In this work non-circular lateral pin-diodes oriented perpendicular to the wafer flat were produced in a scalable, CMOS-compatible process. Electrical characterization revealed that 97% of the devices on an a-plane wafer with n-type epitaxial layer were functional, exhibiting breakdown voltages exceeding 200 V and reverse currents below 100 pA/µm, enabling low current noise during optical measurements. The diodes remained operational at cryogenic temperatures after frozen-out charge carriers were re-ionized by the applied electric field. Electron irradiation followed by thermal annealing at 600 °C was used to generate V2 silicon vacancies in the intrinsic region without significantly altering the electrical characteristics. Optically detected magnetic resonance (ODMR) measurements on selected single emitters confirmed the presence of V2 centers by detecting a contrast at 70 MHz, while cryogenic photoluminescence (PL) spectra revealed a zero-phonon line (ZPL) peak at 916 nm.

Abstract: Silicon vacancies (V_Si) are relevant for quantum technologies, including sensing, computing, and communication. For the realization of quantum photonic integrated circuits (QPICs) and, therefore, co-integration of optical and electrical devices with resonant excitation through the wafer surface, a-plane 4H-SiC wafers are required. Transferring established complementary metal-oxide-semiconductor (CMOS)-compatible processes from c-plane to a-plane wafers is, therefore, a crucial step. In this work, key fabrication steps, namely ion implantation, thermal oxidation, and ohmic contact formation, were investigated for a-plane 4H-SiC substrates. To demonstrate successful process transfer, p-channel MOS field-effect transistors were fabricated and electrically characterized, showing comparable I_on/I_off ratios and mobilities to their c-plane counterparts, but with a threshold voltage shift from −7.1 V to −12.0 V on the a-plane. Additionally, tunneling diodes were realized as broadband light emitters, with a significant portion of the emission spectrum falling within the range of off-resonant excitation of V_Si centers. The devices maintained light emission functionality down to cryogenic temperatures.

Abstract: This study evaluates the performance and reliability of SiC n-and p-MOSFETs across a temperature range from room temperature up to 400°C, focusing on field effect (FE) mobility and threshold voltage variations under high thermal and bias stress conditions. By analyzing the variations in field effect mobility and threshold voltage under different stress conditions, our study illustrates distinct behaviors between devices with thermally grown oxides and those with chemical vapor deposited (CVD) oxide layers, underscoring significant differences in long term performance. Results indicate that while n-MOSFETs maintain threshold voltage shifts below 3% and exhibit robust characteristics up to 400°C, p-MOSFETs exhibit permanent threshold voltage shifts of up to 10% and mobility reductions of 15% particularly above 300°C DC stress. The 2 nm ultrathin thermal (UT) followed by 40nm CVD SiO₂, outperform thermal oxides, sustaining less degradation in mobility and less shift in threshold voltage under bias temperature instability (BTI) conditions at voltages up to ±25V and temperatures as high as 400°C. This research advances SiC CMOS technology by confirming that SiC n-MOSFETs are ready for high-temperature circuit applications, while highlighting the need for further improvement in p-MOSFETs to enhance their reliability under extreme conditions.

Abstract: In this study, we developed an ion implantation process to create a P-type junction isolation (P-iso) structure, which effectively isolates CMOS and 1700-V VDMOSFET devices on a single 4H-SiC wafer. To ensure a sufficiently high blocking voltage and to prevent punch-through or reach-through in all p-n junctions during operation, Sentaurus TCAD was used to optimize the conditions for the P-well, N-well, P-iso region, and multi-floating zone (MFZ) design. A high-energy ion implantation, reaching up to 2.5 MeV, was then conducted to verify the breakdown voltage (V_BD) of the P-iso and MFZ structures. Experimental verification confirms a breakdown voltage (V_BD) exceeding 2000 V.

Abstract: In this study, we numerically compare the characteristics of Si and SiC CMOS operational amplifiers (OpAmp) using LTspice. According to prior researches, we set the device parameters for Si and SiC MOSFETs. The OpAmp consists of three stages: the input stage, the gain stage, and the output stage. We established three criteria for the OpAmp's operation: (1) a unity gain frequency of 1MHz, (2) an open-loop gain of at least 75dB, and (3) a phase margin of more than 60° when a load capacitance is 300pF. To achieve a unity gain frequency of 1MHz, we adjusted the values of the resistor and capacitor used for phase compensation. The supply voltage was set to be ±5V for the Si OpAmp and ±15V for the SiC one. Our numerical analysis of the frequency response shows that the Si OpAmp met all three criteria. In contrast, the SiC OpAmp, when faced with a load capacitor of 300pF, had a phase margin of 43.4°, falling below the 60° mark. For the SiC OpAmp, the frequency response declined rapidly when the supply voltage dropped to 10V or below.

Abstract: This article presents an innovative approach to achieve a high channel mobility for 4H-SiCp-MOSFET via dielectric-semiconductor interface engineering involving atomic layer deposition(ALD) of ultrathin B₂O₃ and SiO₂ stacks. The application of ultrathin boron oxide via ALD introducesa highly manufacturable solution for the passivation of SiC interface. The interface states near valenceband reduces the channel mobility for SiC p-MOSFETs and increases the threshold voltage. Theintroduction of ultrathin B₂O₃ interlayer reduces the threshold voltage and improves the field effectmobility to 12.60 cm²/Vs while the p-MOSFET without the interlayer provides the mobility of 8.91cm²/Vs. This work also includes the optimization of the post-deposition annealing (PDA) conditionsspecific to ultrathin B₂O₃ and bulk SiO₂ dielectric stack to obtain high field effect channel mobilityfor SiO₂/SiC p-MOSFETs.

Abstract: In this paper, a suitable process technology is employed to fabricate a new open gate silicon carbide-based junction field-effect transistor (OG-4H-SiC-JFET) intended to be used for all types of biochemical sensing applications. The main focus is dedicated to the fabrication steps and specifically the plasma etching of the SiC as it is the key step to pattern the device components. All necessary I-V characteristics (I_DS-V_DS and I_DS-V_GS) have been derived and show acceptable electrical performance. Furthermore, the electrical characteristics of the OG-4H-SiC JFET were simulated using 3D Silvaco ATLAS and are in line with the experimental electrical characteristics. The efficacity and simplicity of the process described in this paper is the first step for future development of biochemical sensors based on SiC-FETs.

Abstract: SRAM (Static Random Access Memory) is an essential component of memory devices such as laptops, phones, etc., which act as a semiconductor memory. The “Carbon Nanotube Field Effect Transistor (CNTFET)” is silicon associated high-stability, low-power device with excellent performance. CNTFET has been verified to be very advantageous for Very large-scale integration circuit designs in the nanoscale range because of its remarkable properties of metal oxide semiconductor field effect transistor (MOSFET). The material was brought to light because of its genuinely incredible electrochemical performance. Carbon nanotubes have unique properties such as high charge carrier mobility, high voltage, small footprint, exceptionally short and high control over pulse duration, and large current densities. In traditional MOSFET, bulk silicon is used, which has high leakage current and high field-effect; thus, CNTFET has been used as an alternative in recent years. When compared to the 10T CNTFET SRAM Bit cell is designed using HSPICE Tool in 22nm technology. Long-term stability and significant process variable changes are significant challenges with nanoscale SRAM cells.

Abstract: The characteristic pinched hysteresis behavior of memristors has been reported by stacks of a variety of materials. This paper aims to examine the principles of logic design using such two terminal memristive systems for high performance digital circuit applications. As against logic design with standard CMOS, the benefits of logic design with memristors have been stated. The realization and operation of memristor based AND and OR hybrid logic gates obtained by integrating memristors with standard CMOS logic have been discussed. The IMPLY and MAGIC logic families have been demonstrated by covering MAGIC NOR and NAND logic gate implementation with MAGIC NOR in detail. A qualitative comparison has been drawn towards the end of the paper to conclude on the suitability and application space for each of the logic families studied in this paper. This work also describes the hybrid CMOS-memristive logic family known as MRL (Memristor Ratioed Logic). With the addition of CMOS inverters, this logic family's OR and AND logic gates, which are based on memristive components, are given a full logic structure and signal restoration. The MRL family, in contrast to earlier memristor-based logic families, is compatible with conventional CMOS logic.

Abstract: Radiation detection method has been developed through years. It started from the complex module tools to simple handheld instrument. Recently, the more ease method has been developed with the help of smartphone application. To detect radiation using smartphone usually required the external tools connected to the phone as detector, but there is one application that did not. This application only required complementary metal-oxide semiconductor (CMOS) part of camera. The application is a game changer in radiation protection because nowadays smartphone is in everyone’s pocket. The application needs to be tested to ensure its effectiveness to detect radiation. The application has been tested by the previous research and it is effective to detect radiation. In this research, CMOS will be tested to detect radiation leakage of x-ray tube. The aim of this research is to find the effectiveness of CMOS in smartphone for radiation leakage detection of x-ray tube. The finding will help the radiation worker detect leakage radiation of x-ray tube using smartphone in case of the absences of surveymeter in the facility. The radiation from x-ray machine were detected and measured three times by Iphone 6s, Xs, and 11 using RadioactivityCounter. To ensure there was a leakage, surveymeter is used as a comparative modul. The data obtained from the experiment was analyzed using t-test. The result show that percentage error of Iphone 6s, Xs, and 11 Consecutively were 93.4%, 98.2%, and 98.9%. which mean CMOS in these said phone could detect and measured radiation ineffectively. This due to the low leaked intensity x-ray that came from x-ray machine. From the T-test anaysis found that only Iphone 11 had linear comparison to surveymeter