Papers by Keyword: CMOS

Abstract: The channel material of a gate describes the operating condition of the MOSFET. A suitable operating condition prevails in MOSFETs if the transistors are quite enough to observe and control at the nanometer regime. An efficient gate and channel material have been proposed in this work which is based on the electrical properties they exhibit at the temperature of 300 K. The doping concentration for the electrons and holes is maintained to be 1Χ10¹⁹cm^-3 for the entire electronic simulator. The simulation results show that using La₂O₃ along with Indium Nitride (InN) material for the designing of Double-Gate (DG) MOSFETs provides better controllability over the transistor at a channel length of 50 nm. This proposed DG-MOSFET is more compliant than the conventional coplanar MOSFETs based on Silicon.

Abstract: We modified the active layout of an operational amplifier (op-amp) to exhibit high gamma irradiation resistance of over 100-kGy using our 4H-SiC complementary MOS technology, which can be applied for measuring instruments installed in nuclear power plants. The op-amp with the modified active layout features both a thin gate oxide and newly developed gate-electrode structure for suppressing the leakage current. From an experiment we conducted, the leakage current of the p-channel MOSFET with modified active layout remained unchanged from the initial value after irradiation, although that of it with the conventional layout we previously evaluated increased by about two orders of magnitude. The offset voltage of the improved op-amp was maintained below 2.8 mV up to 100-kGy irradiation. The improved op-amp also showed a healthy amplification characteristic without distortion.

Abstract: Gate All-Around (GAA) is considered a key design feature for future CMOS technology. SiGe vs. Si selective etch is required for Si nanowire formation in GAA. It is confirmed the selective SiGe removal with commodity chemical (mixtures of hydrofluoric acid (HF), hydrogen peroxide (H2O2) and acetic acid (CH3COOH, HAc)), however the thick oxidized layer on Si NW was observed after commodity chemical process, which is indicated the significant Si NW loss. On the other hand, the formulated mixture ACT® SG-101, which is focusing on SiGe oxidizer, chemical pH, solvent polarity & corrosion inhibitor for chemical concept, was performed higher selectivity and lower Si loss than commodity chemical. The formulated mixture has also been used to form an inner spacer for cavity etch scheme and confirmed uniform cavity etch and inner spacer filling on topological test structure.

Abstract: The fabrication of CMOS devices in SiC is important for both a higher operating temperature capability and the integration with SiC power devices. In this work, n-channel and p-channel signal MOSFETs have been successfully fabricated using a process technology fully compatible with our HV SiC VDMOS technology. A preliminary SiC CMOS inverter has been also integrated. The gate oxide configuration includes the use of Boron to improve SiO₂/SiC. Electrical characterizations have been carried out at room temperature and a summary of the results is presented. The biggest challenge is to balance the n-type and p-type MOSFETs not only in area but also in V_th value.

Abstract: The operational amplifier (op-amp) with high gamma irradiation capability of over 30 kGy have been fabricated by 4H-SiC MOSFETs for measuring instruments which are installed in nuclear power plants. The chip size was 0.7 mm x 1.0 mm, and they consisted of five n-channel MOSFETs and three p-channel MOSFETs on the same die. The output waveform after having irradiated 50 kGy at a rate of 60 Gy/hr was amplified without distortion. On the other hand, the offset voltage became unstable when gamma integral dose was beyond 30 kGy and it at 50 kGy increased to +7.2 mV. For reduction of gamma irradiation influence, we proposed the MOSFETs structure which has field plate (FP) electrodes connected to isolation layer electrically. We indicated that the proposal device had the potential of gamma irradiation capability of 100 kGy experimentally.

Abstract: A high-temperature silicon carbide power module using CMOS gate drive technology and discrete power devices is presented. The power module was aged at 200V and 300 °C for 3,000 hours in a long-term reliability test. After the initial increase, the variation in the rise time of the module is 27% (49.63ns@1,000h compared to 63.1ns@3,000h), whilst the fall time increases by 54.3% (62.92ns@1,000h compared to 97.1ns@3,000h). The unique assembly enables the integrated circuits of CMOS logic with passive circuit elements capable of operation at temperatures of 300°C and beyond.

Abstract: For the Ge nanowire formation in a gate-all-around (GAA) integration scheme, a selective etch of Si_0.5Ge_0.5 or Si_0.3Ge_0.7 selective to Ge is considered. Two wet process approaches were evaluated: a boiling TMAH as a commodity chemistry is compared with a formulated chemistry using a multi-stack SiGe/Ge layer as a test vehicle. The boiling TMAH exhibits an anisotropic etch of the SiGe whereas the formulated semi-aqueous chemistry removes the sacrificial SiGe by an isotropic etch which makes the process suitable for a Ge nanowire release process.

Abstract: This paper describes multi-band low noise amplifiers (LNAs) utilizing input matching transformers. We investigate a conventional dual-band LNA circuit utilizing a transformer, and show our analysis and simulation results for its circuit. Based on this, we propose a triple band LNA with transformers. We have calculated characteristics of the dual-band and triple-band LNAs. As the results, the LNAs show gain of 20dB while maintaining good input matching, in the frequencies at 2.59GHz, 3.50GHz and 5.41 GHz. Then we discuss configuration and design of coupling coefficients of the transformers.

Abstract: We demonstrate the influence of enhancing the dielectric film used to form the gate in complimentary MOS circuits, designed for high temperature operation. The data show that the characteristics of both n-MOS and p-MOS capacitors and transistors have degraded capacitance characteristics in terms of the trapped charge in the dielectric, although the interface state density is dictated by the underlying stub oxide, at around 5×10¹² cm^-2eV^-1. The use of a deposited oxide also reduces the variability in the critical electric field in the oxide, whilst maintaining a value of approximately 10MV cm^-1. The channel mobility extracted from n-and pMOS transistors fabricated alongside the capacitors showed similar values, of approximately 3.8 cm²V^-1s^-1, which are limited by the high doping level in the epilayers used in this study.

Abstract: In this work, the impact of the n-well doping concentration on the channel mobility and threshold voltage of p-MOSFETs and their applications in CMOS-devices is evaluated. For this purpose lateral p-channel MOSFETs with different channel lengths (L = 800 μm, 10 μm, 5 μm, and 3 μm) and doping concentrations (N_D = 10¹⁵ cm^-3 and 8·10¹⁵ cm^-3) were fabricated and the respective field-effect mobility was extracted from the transfer-characteristics. Comparable to n-MOSFETs the mobility of p-MOSFETs was found to be the highest for the lowest doping concentration in the channel and the absolute value of the threshold voltage increases with increasing doping concentration [4]. To investigate its suitability for CMOS applications, inverters with different doping concentrations for n-MOSFET (N_A = 10¹⁵ cm^-3 and 10¹⁷ cm^-3) und p-MOSFET (N_D = 10¹⁵ cm^-3 and 8·10¹⁵ cm^-3) were built. For logic levels of 0 V and 10 V, the voltage transfer characteristic with the highest input ranges was obtained for a low p-MOSFET and a high n-MOSFET doping concentration. The lowest propagation delay time could be achieved with a low p-MOSFET and a low n-MOSFET doping concentration. At room temperature as well as at high temperatures T = 573 K the drain current of p-MOSFETs with channel lengths below 3 μm is hampered by the series resistance of the source and drain region which limits the performance of CMOS devices.