Papers by Keyword: CMOS Process

Abstract: In this paper, a low-voltage automatic gain control (AGC) circuits is presented. The proposed circuit uses a novel approximated exponential function to increase the dB-linear output range. The three-stage AGC is fabricated in 0.18μm CMOS technology and shows the maximum gain variation of more than 100dB and a 67dB linear range with linearity error of less than ±1dB. The range of gain variation can be controlled from 34 to 101dB. The AGC dissipates less than 2.3mA under 1.8V supply voltage while occupying 0.4mm² of chip area.

Abstract: A CMOS compatible absolute pressure sensor with extend floating gate is developed with simple circuitry to realize high sensitivity, linearity, and manufacturability. The pressure sensitive membrane formation is based on the standard CMOS process with simple metal sacrificial layer removal step, which is very cost-efficient and fully CMOS compatible, enabling monolithic integration of circuitry. ANSYS and SPICE simulation results show that the proposed sensor can worked properly under 500K Pa, and the square sensing membrane of 100x100 μm ² shows a good linearity over a pressure change ranging from 5 Pa to 500K Pa.

Abstract: The paper is presented the design of high-frequency OTA-C band-pass filter with on-chip automatic tuning. In this design, the linear operational transconductance amplifier (OTA) is proposed based on fully complementary differential pairs with source degneration, and achieves both low-distortion figures and high-frequency operation. The matching design between the master filter and the slave filter is also given, and the non-ideality effect of the OTA-C filters with on-chip automatic tuning is discussed. The whole circuit is designed using TSMC 0.18μm 1.8V CMOS process and post-simulation results show the center frequency of filter is 105MHz with relative error of 0.4%, when the process corner varies between SS, TT, FF, and the temperature from-20 to 120°C.

Abstract: ^{Superscript text}Thermopile-type Infrared detector is more and more popular in many fields, including infrared spectroscopy, radiometry, security systems and many consumer products. This paper reports a novel n-poly/p-poly thermopile suspension structure with four pairs of thermopiles that compatible with Complementary Metal-Oxide Semiconductor (CMOS) technology and its fill factor is larger than 90%. No additional material is needed to enhance infrared absorption since the passivation layer provided by the CMOS process is sufficient for certain infrared spectral bands. With the selected material parameters the optimal structure parameters are obtained after simulation. Through the theoretic calculation, this novel IR detector has good properties of high responsivity (larger than 1000V/W) and detectivity (larger than 1×108cm Hz1/2W-1) and low response time (shorter than 30ms).

Abstract: In this paper, the design of a CMOS transceiver circuits for CAN bus based on 0.5μm n-well CMOS process is presented. It has the advantages of high speed, high driving capability and strong anti-interference capability. It is mainly made up of a receiver and a transmitter which includes the input stage circuit, the middle stage circuit, the slew rate control circuit and the output stage circuit. With five cascaded inverters, the middle stage circuit can provide a high driving current and a small delay. In the slew rate control circuit, due to a variable charge or discharge current source, the slew rate of output signal could be adjusted continuously by an external resistance Rs. So it is very convenient for the chip to be applied in different modes and at different rates. The output stage circuit has the function of short-circuit protection, overvoltage and undervoltage protection. The receiver circuit is a hysteresis comparator introduced by a positive feedback to reduce the differential noise effectively, and it has a small temperature coefficient too. Hspice simulation results show that the transceiver meets the ISO-11898 standards and could operate at the rate of 1Mbit/s.

Abstract: This paper describes a low-power 1.2 V 8-bit 1Gs/s two-channel pipeline ADC. The novelty of the designed ADC lies in: ameliorating the two-channel pipeline structure that consists of 1.5-bit multiplying DAC (MDAC). In order to reduce the power consumption and improve the sampling speed, the dual-channel pipeline Time Division Multiplexing operation amplifier and double or single channel flash ADC are used; in the front-end Sample-and-Hold circuits, switch-linearization control circuits(SLC) driven by a single clock signal is applied to solve the problem of time-skew and time mismatch between two channels. The pipeline ADC is designed with 90 nm CMOS process. From the simulation results of the designed ADC, we can draw that the SFDR is 42.3 dB; the SNR is 32.7 dB under the usual temperature. The ADC achieves 21 mW power-dissipation, 8 resolution and 1.01 GS/s sampling speed. So the design meets high speed, high precision and low power dissipation at the same time.

Abstract: The standard Local Oxidation of Silicon (LOCOS) technique uses different oxidation rates of silicon and Low Pressure Chemical Vapour Deposited (LPCVD) silicon nitride in steam ambient to structure the field oxide. Due to different coefficients of thermal expansion a pad oxide is needed at the boundary layer to prevent stress from the substrate. This leads to a lateral diffusion of oxygen, also known as “birds beak”, which limits the minimum structure size to a few 100 nm [1]. When scaling down to this dimension, the Shallow Trench Isolation (STI) has become the standard isolation technique for fabrication of high-performance semiconductors to allow a high package density. Unfortunately the STI-process uses Chemical Mechanical Polishing (CMP) which increases the process complexity and leads to high costs. Therefore a new method which uses a low stress Plasma Enhanced Chemical Vapour Deposited (PECVD) silicon nitride without a pad oxide at the boundary layer will be presented in this paper.