Papers by Keyword: CRC

Abstract: This paper describes the algorithm principle of CRC-32 codes, and then proposes multiple bits parallel input to achieve CRC-32 checksum on the basis of the principle. To design modules using VHDL language in Quartus II environment based on Altera’s EP4SGX230KF40C2 chip. Compared to traditional method of serial and 8 bits parallel data input, implementation of the program integrates 16, 32 and 64 bits parallel data input modes, the user can select the appropriate modules according to their needs and environmental constraints, which will greatly enhance the ability to adapt to the system and meet the needs of a variety of environments.

Abstract: Automatic Dependent Surveillance Broadcast (ADS-B) system signal error detection and correction process scheme are introduced in this paper, and the working principle of cyclic redundancy check (CRC) is described. Then, this paper provides an error correction algorithm based on the confidence judgment and an error correction process flow chart based on ADS-B system. Finally, the design of CRC checksum is performed by taking use of Verilog HDL, and the simulation and verification are achieved in Modelism software platform. Experimental results show that the algorithm can carry out verification and error correction for ADS-B responding signal and can improve the reliability of ADS-B system signal transmission.

Abstract: The article introduced the basic data construction of RDS and how to use hardware and software combination to achieve RDS data reception and processing. Subcarrier demodulation is completed by ASIC that outputs RDS pulse signal to the decoding MCU. Discuss focuses on fast and efficient RDS signal sampling and processing. The algorithm is concise and easy to implement, so common MCU can complete the input data synchronization, verification and valid data extraction.

Abstract: This paper proposes a new synchronized serial-parallel CRC(Cycle Redundancy Check) with PIE(Pulse Interval Encoding) decoding circuit for the UHF(Ultra-High Frequency) RFID(Radio Frequency Identification), which is based on the ISO/IEC 18000-6C standards protocol. The parallel algorithm of CRC circuit is derived, and the serial or parallel CRC circuit on RFID tag chip is evaluated in this paper. Finally, the designed circuit is simulated and analyzed on the FPGA platform. Simulation results show that the proposed circuit meets the communication requirement of the protocol and addresses the problem of low data processing rate of conventional serial CRC circuit, as well as implements 1 to 8 degree of parallelism of the parallel CRC circuit for UHF RFID.

Abstract: Aiming at solving the problems of occlusion and illumination in face recognition, a new method of face recognition based on Kernel Principal Components Analysis (KPCA) and Collaborative Representation Classifier (CRC) is developed. The KPCA can obtain effective discriminative information and reduce the feature dimensions by extracting faces nonlinear structures features, the decisive factor. Considering the collaboration among the samples, the CRC which synthetically consider the relationship among samples is used. Experimental results demonstrate that the algorithm obtains good recognition rates and also improves the efficiency. The KCRC algorithm can effectively solve the problem of illumination and occlusion in face recognition.

Abstract: The common method of implementing a HDLC controller is either using an ASIC device or designing it with software. It is easy to implement a HDLC controller with an ASIC device, but it is hard to modify it. The software method introduces a flexible way, but it will occupy a huge amount of CPU resource, and the timing parameters are hard to ensure. Designing HDLC controller with FPGA can take advantage of both speed and flexibility, furthermore, with the programmable ability of FPGA, more than one channel can be implemented in a single FPGA. This paper introduces a HDLC controller design base on Alteras Cyclone III FPGA and Quartus II developing environment. The controller contains four HDLC channels and an interface for PC104 bus. Except the basic HDLC protocol, more functions are added into the controller, such as alterable flag sequence, built-in timer and so on. The design has been fully tested, and has been used in a communication production successfully.

Abstract: By introducing the basic principle of ordinary CRC algorithm, the paper develops an algorithm which can be used to analyze data communication structure and construct design process. At the same time, it can be quickly implemented in the data communication process. The algorithm uses Verilog HDL hardware description language to complete all the design on ISE development platform. And it uses Xilinxs development board Virtex-II Pro to achieve the final realization. Compared with traditional methods, the algorithm is simple and intuitive, which reduces computational the delays and saves space. It also benefits hardware implementation.

Abstract: This work proposes a CRC-aided K-best sphere decoding scheme to improve the performance of lattice codes. The generator of the lattice is designed as to be an upper triangular, which is naturally suited for sphere decoding. When the K is sufficiently large, the naïve K-best sphere decoding can approach the lower bound of block error rate (BLER) of maximum likelihood (ML). Therefore, the proposed scheme can outperforms the naïve K-best sphere decoding with the assistance of CRC code.

Abstract: This paper has designed data transmission system of logging cable based on CPLD and DSP. This system realizes the function of modulation and demodulation in BPSK with CPLD, in which the application is flexible and the circuit is simple and reliable. The System uses DSP to realize the checking function of software CRC, improving the stability and reliability of data transmission. Practical application shows that the system works normally with stable and reliable performance and can meet the requirements of the transmission of conventional logging.

Abstract: In order to avoid the digital humidity & temperature sensor SHTxx’s output values conversion consume many quantity of storage location, and spend more operation time, a group new type of conversion polynomials, and corresponding programming algorithm were deduced and tested. The polynomials are precise equivalent to the conversion formulas provided by the manufacturers, but contain only Binary fixed-point integer, fractional part, and 2N. Using fixed-point calculations and shift operations instead of floating-point calculations, the results of program code reduction amount of 60 percent, and computing speed faster nearly 4 times than the original algorithm are obtained. Furthermore, a kind of speedy and unified CRC algorithm for read-out data of the sensor is proposed. The novel programming algorithm makes the output conversion more simplified, so it could pave the way for the low-end embedded applications of SHTxx.