Papers by Keyword: Capacitance Voltage

Abstract: Modest channel carrier mobility in SiC-MOSFETs with NO annealed gate oxides has been the main factor hampering development of low power devices (300 – 650 V). A very fast interface trap, noted as NI, has been suggested to be the main culprit for poor inversion channel carrier mobility. The origin of the NI trap is unknown, but it is likely a property of the SiO₂ and it is enhanced during post nitridation. In this study we show that the NI trap is also detected in 4H-SiC/AlN and 4H-SiC/Al₂O₃ MIS-capacitors. Observations are done using conductance spectroscopy and capacitance voltage measurements at cryogenic temperatures. This strongly suggests that the NI trap is a property of the SiC surface and not the dielectric used to form the SiC/dielectric interface. Furthermore, a scanning transmission electron microscopy (STEM) was performed to confirm that there are no SiO₂ layers or islands present at the 4H-SiC/AlN and 4H-SiC/Al₂O₃ interfaces.

Abstract: The channel carrier mobility in commercially available 4H-SiC MOSFETs with NO annealed gate oxides is still far below the theoretical limit. It has been suggested that the main reason is high density of very fast interface traps, labeled NI, located inside the oxide very close to the SiC conduction band edge. The NI traps are usually not observed at room temperature but can be detected at cryogenic temperatures. In this study we use conductance spectroscopy and high-low CV analysis of MOS-capacitors at cryogenic temperatures to show that the very fast NI traps are practically absent in oxides grown using sodium enhanced oxidation.

Abstract: The excellent material properties of the wide band gap semiconductor SiC are accompanied by challenges in device processing. Of particular importance is the incomplete activation of implanted Al acceptors after high-temperature annealing. In this work, we present a novel approach in applying the differential-capacitance method to lateral MOS capacitors, where systematic errors in its characterization are reduced by introducing a buried current-spreading layer. We find that the implantation of an additional current-spreading layer significantly reduces series resistance effects and enables a reliable capacitance-voltage measurement of low dopant concentrations of p-type wells in n-type epitaxial layers. The measurement of an Al box-like profile implanted at 500 °C and resulting in a doping concentration of 3·10¹⁷ cm^-3 shows full activation after annealing at 1800 °C for 30 minutes.

Abstract: A model to explain forward bias capacitance-voltage measurements is presented and compared with experimental results. Forward bias capacitance-voltage measurements, with environment light, were performed in a sample containing CdSe ultra thin quantum wells periodically embedded on undoped epitaxially grown ZnSe on a semi-insulating GaAs(001) substrate. A Au Schottky contact and annealed Ti/Pt/Au ohmic contacts were deposited on the sample surface in a coplanar cylindrical geometry. Under this model both type of carriers are necessary to explain the capacitive (holes) and resistive (electrons) behaviors. The measurements are fitted following the presented model, reasonable agreement is obtained. The quality factor Q is calculated and it is found to be smaller than one, hence no correction is needed. The charge carrier density profile is done on the capacitance voltage measurement. The experiments indicate a periodic charge distribution in the samples attributed to charge captured in the ultra thin quantum wells.

Abstract: 4H Silicon Carbide (4H-SiC) has a great potential for low-loss power devices due to its superior electrical properties. However, the increase in demand for the power devices requires high quality SiC substrates and epitaxial layers. Mercury probe Capacitance Voltage (Hg CV) measurement is a well known procedure to characterize epi layers grown on SiC substrates, due to its non-destructive technique. However, careful calibration of the tool is very important for repeatable and accurate measurements. Here we present very close repeatability of Hg CV within 2.4% (standard deviation 0.7%), between different Solid State Measurements (SSM) setups compared with Ni Schottky (NiS) CV. In addition to growing uniformly doped epi layers, high surface quality of the epi layer is also needed for improved device performance. Improved process conditions resulted in a smooth epi with a surface roughness Ra 1.2 nm for a 6 µm thick epi layer. Molten Potassium Hydroxide (KOH) etching analysis also revealed a significant correlation between the surface roughness and epi defects.