Authors: Yasuyuki Igarashi, Kazumi Takano, Yohsuke Matsushita, Takuya Morita
Abstract: The reliability issue of the bipolar degradation in 4H-SiC devices has not been completely eliminated. We have been proposing a screening method for latent defects causing this reliability issue utilizing UV irradiation, which we call the E-V-C (Expansion-Visualization-Contraction) method. This method is based on the property that the REDG (recombination-enhanced dislocation glide) mechanism that causes the bipolar degradation can be reproduced by UV irradiation. However, in order to apply this method as a screening method, accurate quantification of the correlation between current density in forward bias and UV irradiance is required. In this article, we estimated the extent to which the carrier lifetime of the sample affects the quantification of the correlation and found that it had a non-negligible degree of influence on the correlation. Then, we tried to find if there is a simple method for estimating carrier lifetime that can be incorporated in the screening process, and report on our attempts in progress.
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Authors: Hidetsugu Uchida, Motoki Kobayashi, Naoki Hatta, Seiji Ishikawa, Yuta Higashi, Hiroshi Sezaki, Shinsuke Harada, Kazutoshi Kojima
Abstract: In this study, we investigated the generation of trap centers through hydrogen implantation to understand its role in the suppression of forward bias degradation in 4H-silicon carbide (4H-SiC) bonded substrates. During the production of bonded substrates, hydrogen implantation is used for layer splitting. Transmission electron microscopy (TEM) observations revealed that the basal plane dislocation (BPD) in the bonded substrate did not extend into the Shockley-type stacking fault (SSF) and remained stable in the transferred layer below the epitaxial interface even under high forward current stress. Additionally, carrier lifetime, measured using microwave photoconductivity decay (μ-PCD), was considerably reduced by hydrogen implantation. Annealing at 1700°C reduced the implanted hydrogen to levels below the detection limit of secondary ion mass spectrometry (SIMS), yet the carrier lifetime remained short. Deep level transient spectroscopy (DLTS) revealed that, after annealing at 1700°C following hydrogen implantation, the concentration of the Z1/2 center increased by more than two orders of magnitude compared to pre-implantation levels. Trap centers, including the Z1/2 center, are believed to help prevent forward bias degradation in the bonded substrates by inhibiting the expansion of SSFs in the transferred layer.
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Authors: Hitesh Jayaprakash, Constantin Csato, Masashi Kato, Tong Li, Florian Krippendorf, Michael Rueb
Abstract: Bipolar degradation poses a significant concern for the reliability of SiC bipolar power devices. The basic cause for bipolar degradation is expansion of Shockley Stacking Faults SSFs. These glide planes can be pinned and prevented from expansion. This study involves 19 MeV Energy Filtered Ion Implantation of Nitrogen (i.e. resulting in an energy spectrum ranging from 0 MeV to nearly 19 MeV in one shot) to explore the pinning effect of Nitrogen ions that suppresses recombination glide, which minimizes SSF growth, while providing precise doping of the entire drift region by the same Nitrogen implantation. All is performed in one single step. This procedure paves the path to immobilize any nucleation sites in the entire drift layer, this way enhancing the reliability and facilitating mass production of SiC power devices. This study employs UV illumination as an optical stressing method to create e-/h+ pair, which subsequently induce 1SSF expansion. Both, UV induced 1SSF expansion and pining were observed by photoluminescence. Carrier lifetime measurements were employed for understanding the mechanism of pinning defects.
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Authors: Hideyuki Uehigashi, Takeshi Okamoto, Akiyoshi Horiai, Hiroaki Fujibayashi, Takahiro Kanda, Takashi Kanemura, Kazuhiro Tsuruta
Abstract: In order to increase productivity and reduce the cost of wafers, we have developed a high temperature chemical vapor deposition (HTCVD) method that can realize the high-speed growth of 4H-SiC crystals. Tokuda et al. reported an interesting study in which the carrier lifetime of a substrate grown by HTCVD (HTCVD substrate) was considerably shorter than that of the substrate grown by physical vapor transport (PVT); moreover, bipolar degradation was highly suppressed when the HTCVD substrate was applied to PiN diodes [1]. Herein, we demonstrate that the short carrier lifetime of the HTCVD substrate is mainly attributable to the carbon vacancy (VC) and that VC particularly diffuses from the HTCVD substrate to the epitaxial layer.
13
Authors: Lu Yang Zhang, Tian Xiang Dai, Peter Michael Gammon, Neophytos Lophitis, Florin Udrea, Amit Tiwari, Jose Ortiz-Gonzalez, A. Benjamin Renz, Vishal Ajit Shah, Philip Andrew Mawby, Marina Antoniou
Abstract: The commercial success of silicon carbide (SiC) diodes and MOSFETs for the automotive industry has led many in the field to begin developing ultra-high voltage (UHV) SiC insulated gate bipolar transistors (IGBTs), rated from 6 kV to 30 kV, for future grid conversion applications. Despite this early interest, there has been little work conducted on the optimal layout for the SiC IGBT, most early work seeking to overcome difficulties in fabricating the devices without a P+ substrate. In this paper, numerical TCAD simulations are used to examine the link between the carrier lifetime of SiC IGBTs and their short circuit capability. For the planar devices, simulations show that increasing carrier lifetime from 1 to 10 μs, has not only a profound effect reducing on-state losses, but also increases short circuit withstand time (SCWT) by 39%. Two retrograde p-well designs are also investigated, the optimal device for SCWT having a 100 nm channel region of 5×1016 cm-3, with this increasing to a peak value of 2×1018 cm-3, in a 700 nm region beneath the channel.
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Authors: Alessandro Meli, Annamaria Muoio, Riccardo Reitano, Antonio Trotta, Miriam Parisi, Laura Meda, Francesco La Via
Abstract: In the present work a deep characterization of 4H-SiC epi-layer was done. A thick layer was epitaxially grown through chemical vapor deposition (CVD) process in a horizontal hot-wall reactor in order to obtain a 250 microns thick epi-layer. This sample will be used as particle detector in hostile environments such as neutron detection in a nuclear fusion reactor. Raman and Photoluminescence (PL) spectroscopy have been used in order to evaluate the general status of epitaxy and, with the support of the Time Resolved Photoluminescence, also important properties such as carrier lifetime and diffusion length have been evaluated. Carrier lifetime evaluation before and after a thermal oxidation process at 1400° C for 48h was estimated, by considering a lifetime increment after oxidation process, due to the decrease of carbon vacancies. Finally, the influence of stacking fault (SF) defects on carrier lifetime was evaluated observing a decrease of the lifetime for the defects at 430 nm (2.88 eV) for both oxidated and non-oxidated samples.
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Authors: Khaoula Amri, Rabeb Belghouthi, Michel Aillerie, Rached Gharbi
Abstract: Among all the material parameters of a semiconductor, the lifetime of the carriers is one of the most complex, as it is a function of the dominant recombination mechanism, the number of carriers, the structural parameters and the temperature. Nevertheless, the lifetime of the carriers is a very useful and fundamental parameter to be determined for the qualification of the semiconductor in order to allow the improvement of the manufacturing process and the optimization of the operation of the semiconductor device. Thus being strongly linked to many physical and electronic parameters, the lifetime of the carriers cannot be provided only with a theoretical average value and an experimental measured value must be obtained. In the case of semiconductor junctions, precise measurements of the open-circuit voltage decay, OCVD, make it possible to trace the lifetime of the carriers through the device. An automated method for OCVD measurements presented in this contribution overcomes the main limitations that arise in the standard method when used for the characterization of the lifetime of carriers as it achieves the "open circuit conditions" of the device under test and reduces inherent noise of the differential operation mode of the method.
3
Authors: Wen Ting Zhang, Yun Lai An, Yi Ying Zha, Ling Sang, Jing Hua Xia, Fei Yang
Abstract: A novel process is developed for minority carrier lifetime enhancement in ultra-high 4H-SiC PiN diodes. It comprises two separate processes. Firstly, the ultra-thick epitaxial grown drift layer (200μm) covered with a protective thin carbon film is subject to a 1500°C high-temperature anneal process in Ar atmosphere for 2 hours. Secondly, a surface passivation process is adopted to reduce the surface recombination rate. μ-PCD tests show that after high-temperature anneal, the thick drift layer shows a minority carrier lifetime increase to about 1.6 μs. PiN diodes based on the novel process are fabricated and their electric characteristics are measured. Results show a low specific on-resistance of 16.3 mΩ·cm2 at 25°C and 14 mΩ·cm2 at 125 °C. Compared with simulation results, it is shown that its effective minority carrier lifetime increase to about 5μs .Our study demonstrates that the developed novel process is effective in minority carrier lifetime enhancement in ultra-voltage 4H-SiC PiN diodes.
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Authors: Sei Hyung Ryu, Daniel J. Lichtenwalner, Michael O’Loughlin, Craig Capell, Jim Richmond, Edward van Brunt, Charlotte Jonas, Yemane Lemma, Albert A. Burk, Brett Hull, Matthew McCain, Shadi Sabri, Heather O'Brien, Aderinto Ogunniyi, Aivars J. Lelis, Jeff Casady, David Grider, Scott Allen, John W. Palmour
Abstract: High performance 15 kV n-GTOs were demonstrated for the first time in 4H-SiC. The device utilized a 140 μm thick, lightly doped n-type drift layer, with 1450°C lifetime enhancement oxidation, which resulted in a carrier lifetime of 17.5 μs. The p+ backside injector layer was thinned to minimize parasitic resistances. A room temperature forward voltage drop of 5.18 V was observed at a current density of 100A/cm2. A 1 cm2 device showed a leakage current of 0.17 μA at 15 kV. The 4H-SiC n-GTO showed latching characteristics, and showed a turn-off time of 170 ns in a resistive load switching setup, which represents about a factor of 45 improvement in turn-off speed over 4H-SiC p-GTOs with comparable voltage and current ratings.
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Authors: Birgit Kallinger, Jürgen Erlekampf, Katharina Rosshirt, Patrick Berwian, Matthias Stockmeier, Michael Vogel, Philip Hens, Frank Wischmeyer
Abstract: Two fully loaded epitaxial growth runs with 16 wafers in total were conducted in the AIXTRON G5 WW reactor in order to keep epigrowth conditions constant. The wafers were selected with a large spread of specific resistivity and dislocation densities. The resulting epilayers showed very good intra-wafer homogeneities as well as excellent wafer-to-wafer and run-to-run reproducibility with regard to epilayer thickness and doping concentration, point defect concentrations of Z1/2 and EH6/7 and the resulting Shockley-Read-Hall carrier lifetime. We found that the dislocation densities of the underlying substrates are influencing the stacking fault densities of the epilayers, which then vary between 0.1 and 10 cm-2. A substrate effect on the effective minority carrier lifetime was found.
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