Papers by Keyword: Channel Mobility

Abstract: In this paper, we study high-temperature H₂, N₂, and H₂/N₂ surface conditioning processes prior to the SiO₂ deposition as a promising approach for SiO₂/4H-SiC interface preparation in metal-oxide-semiconductor field-effect transistors (MOSFET). A thorough electrical analysis is presented, consisting of temperature-dependent transfer characteristics as well as reliability studies regarding bias temperature instabilities (BTI) and dielectric breakdown behavior. Especially N₂-containing surface pretreatments were found to greatly suppress electron traps, whereas hole trapping is enhanced. Finally, X-ray photoelectron spectroscopy (XPS) was utilized to elucidate the elemental surface composition after the different annealing procedures. The obtained results are in good agreement with the electrical characterization and complement already published results regarding the formation of surface reconstructions on 4H-SiC through H₂ and H₂/N₂ annealings.

Abstract: We present a revised channel mobility model for 4H-SiC MOSFETs. Mobility measurements are performed on 4H-SiC lateral MOSFET test structures in the temperature range of 25-175 °C. We observe that the temperature and P-well concentration dependence of channel mobility cannot be predicted by popular mobility models available within commercial TCAD tools. A careful investigation revels that channel mobility components need to be revised and replaced using a comprehensive model that accurately describes the predominant scattering mechanisms. We present a well calibrated channel mobility model for 4H-SiC using a revised treatment of bulk, surface roughness and surface phonon components. An excellent agreement with measured data is obtained using this model, making it more suitable for predictive device simulation using TCAD tools.

Abstract: The poor quality of SiC/SiO₂ interface significantly limits the channel mobility, especially in 4H-SiC MOSFETs. Several strategies have been addressed to overcome this issue. Nitridation by NO has been adopted widely by manufactures because nitrogen may replace carbon in some chemical bond at the SiC/SiO₂ interface. However, excessive nitridation is not desirable because of pronounced hole-trapping effects near the conduction band. As an alternative gate dielectric, thin SiO₂/deposited oxide stack has been investigated in 4H-SiC lateral nMOSFETs. Overall performances were reviewed in aspects of transfer/g_m/reverse characteristics, charge pumping method and TLP characteristics.

Abstract: A study on the impact of different growth and deposition techniques on the reliability of silicon dioxide (SiO₂) layers on silicon carbide (SiC) metal-oxide-semiconductor capacitors (MOSCAPs) is presented and compared to channel mobilities that were extracted from lateral metal-oxide-semiconductor field-effect transistors (LMOSFETs). Oxide layers were formed using atomic layer deposition (ALD), low pressure chemical vapour deposition (LPCVD) and direct thermal growth, including post-deposition anneals (PDAs) in nitrious oxide and forming gas (FG) for the ALD-and LPCVD-deposited oxides. Electrical characterisation results at elevated temperatures show that a PDA in FG leads to the highest average breakdown electric field of 10.08 MV/cm, outperforming all other device splits. Time-dependent dielectric breakdown (TDDB) results showed that the time to failure of 63% of the investigated samples at 9MV/cm in the FG-annealed samples was about 50% higher than in LPCVD-deposited oxides that had undergone an N₂O PDA. Channel mobilities of the FG-treated samples averaged about three to four times higher than in other datasets, showing excellent peak field-effect mobilities of 60 cm²/V.s and 108 cm²/V.s at room temperature and 175°C, respectively.

Abstract: Silicon carbide (SiC) metal-oxide semiconductor (MOS) power devices such as metal-oxide semiconductor field-effect transistors (MOSFETs) require a stable and low defect-density interface, and a high-quality dielectric, for good device performance and reliability. Notably, the interface and dielectric properties determine the threshold voltage stability, the field-effect channel mobility, and the device lifetime as limited by dielectric breakdown in both the forward on-state and reverse blocking conditions. Here we discuss the present state of SiC MOS processing and properties and point to directions for future development. Important items to address are: 1) interface passivation approaches; 2) dielectrics; 3) device design; and 4) in-depth measurements of the interface quality and reliability.

Abstract: SiC gate-all-around (GAA) nanowire (NW) MOSFET is one of the most promising device architectures for the next generation of SiC power MOSFETs. This work reveals the great application potential of vertical SiC GAA NW power MOSFETs via TCAD simulation. The investigated devices show higher channel electron mobility (µ_ch) and larger channel carrier density (n_ch) compared to the conventional SiC power MOSFET. Scaling down of NW diameter (D_NW) is beneficial in terms of both, lowering channel resistance (R_ch) via improving n_ch and, increasing breakdown voltage (V_b) by modifying electric field distribution. Low specific-on resistance (R_on,sp) of about 0.68 mΩ∙cm² for 1 kV SiC MOSFET is shown as possible. However, scaling down the D_NW below 100 nm causes an undesirable increase in R_on,sp due to the unscalable device area which is limited by the vertical gate wrapping stacks. The study on device scaling where the NW diameter (D_NW) varies from 500 nm to 25 nm provides valuable design considerations for the device's performance. Finally, a top-down process has been developed for the device fabrication. Vertical SiC NWs with an aspect ratio of 10 are formed by an optimized micro-trench free dry etching process.

Abstract: It has recently been shown that interface defect density (D_it) at SiO₂/SiC interfaces can have non-uniform clustered distribution through the measurement by local deep level transient spectroscopy (local DLTS). Here we investigate the influence of the non-uniform D_it clustering on the field-effect mobility in SiC metal-oxide-semiconductor field effect transistors (MOSFETs) by device simulation. We develop a three dimensional numerical model of a SiC MOSFET, which can incorporate actual D_it distributions measured by local DLTS. Our main result is that the impact of the non-uniform D_it clustering on field-effect mobility is negligible for a SiC MOSFET with high D_it formed by dry thermal oxidation but it becomes significant for that with lower D_it by post-oxidation annealing. The result indicates that channel mobility can be further improved by making D_it distribution uniform as well as reducing D_it.

Abstract: We used the POCl₃ gate technique for the fabrication of 4H-SiC vertical MOSFETs, and examined its effect on the V_TH-R_ON tradeoff and the compatibility with device fabrication. The gate oxide film was formed by thermal dry O₂ oxidation followed by POCl₃ or NO annealing. The POCl₃ process reduced R_ON by about 30% compared with the NO process for the ones having V_TH of 1.1 V, being attributed to the channel mobility enhancement. Moreover, the improvement was more effective for higher V_TH designs. The conventional thermal treatment after the gate process considerably spoiled the channel mobility improvement brought by the POCl₃ annealing and strengthened negative charge trapping in the gate oxide. The presumed extra-formed defects also affected the E_OX dependence of t_BD on the TDDB tests, being expected to shorten the gate oxide lifetime under practical device operation stress. Successful insertion of the POCl₃ process into production lines depends upon careful low-temperature post processing.

Abstract: In this work, we investigate the effect of borosilicate glass (BSG) as gate dielectric on dielectric/4H-SiC interface traps and channel mobility in 4H-SiC MOSFETs. The interface trap characterization by C−ψs analysis and I-V characterization show lower fast interface trap density (D_it) as well as significant improvement of channel field-effect mobility on devices with BSG than that on devices with standard NO anneal. In addition, the results indicate interface trap density decreases with increasing B concentration at the interface of BSG/4H-SiC, which in turn, results in higher channel mobility.

Abstract: In this work, TCAD modeling of a 1200 V SiC MOSFET is presented. The main focus is on modeling of the channel mobility, and the Coulomb scattering by interface traps and surface roughness are therefore included. For the Coulomb scattering, the interface trap profiles have been extrapolated from the subthreshold characteristics at room temperature, whereas the scattering due to surface roughness has been fitted by comparing to the transfer characteristics at high gate bias. A comparison with measurements for the transfer characteristic and the output characteristic is also presented. Results show that the reduction of the threshold voltage with increasing temperature and the temperature dependence of the output characteristics are properly modeled.