Papers by Keyword: Charge Trapping

Abstract: In this work a reliability study of SiC power MOSFETs working as switching elements in a DC-DC Boost converter circuit is discussed. A critical parameter for a high-performance operation is the stable characteristics of the transistors employed. However, charge trapping effects such as bias temperature instabilities can affect e.g. the threshold voltage of transistors and thus lead to a variation in circuit behavior and efficiency. Furthermore, a time-dependent drift of the threshold voltage (ΔVth) of the MOSFET over time can cause an increase of the on-resistance (RDS(ON)) too, and thus affect the static on-state power losses accordingly (PON). In this work, we use our physical reliability simulator Comphy to extract the threshold voltage drift of the transistor over time for various mission profiles for gate biases under device operation. Using the extracted ΔVth values from the simulator, we can reproduce the measured behavior of the DC-DC boost converter circuit. With the calibrated toolset, we can obtain the ΔVth values over a long operation time to predict the aged behavior of the circuit parameters employing Spice simulations, which could be beneficial for circuit design and lifetime prediction of the system.

Abstract: We show the superior threshold voltage V_th and on resistance R_on stability of a SiC DMOStechnology at bipolar gate-drive operation. Therefore, the defect parameters of a two-state non-radiativemulti-phonon model to capture the charge trapping kinetics of oxide and interface defects is calibratedwithin our simulation framework Comphy by data extracted from measure-stress-measure (MSM) se-quences. An extrapolation of the device degradation at operating conditions renders bias temperatureinstabilities (BTI) a minor threat to on-state loss increase.

Abstract: In the recent past, lots of efforts have been put into further developing SiC power MOSFETs. In addition to optimization of device geometry, i.e., vertical device structure, various post-oxidation anneals have been studied to improve carrier mobility by reducing trap density. Nevertheless, a considerable number of traps remain, which are the central origin for dynamic changes in the threshold voltage of up to several volts during DC and AC operation. To explain the threshold voltage instability, an effective two-state defect model has been recently applied. In this work, we give an overview of modeling efforts to explain the impact of defects on the device threshold voltage and discuss the hysteresis of voltage sweep and bias temperature instabilities in SiC transistors. Based on the combination of measurements and computer simulations, a list of potential defect candidates responsible for the observed threshold voltage instabilities is discussed.

Abstract: Hysteresis response of epitaxially grown graphene nanoribbons devices on semi-insulating 4H-SiC in the armchair and zigzag directions is evaluated and studied. The influence of the orientation of fabrication and dimensions of graphene nanoribbons on the hysteresis effect reveals the metallic and semiconducting nature graphene nanoribbons. The hysteresis response of armchair based graphene nanoribbon side gate and top gated devices implies the influence of gate field electric strength and the contribution of surface traps, adsorbents, and initial defects on graphene as the primary sources of hysteresis. Additionally, passivation with AlO_x and top gate modulation decreased the hysteresis and improved the current-voltage characteristics.

Abstract: For the analysis of the characteristics and behavior of circuits prior to fabrication and to improve circuit performance, simulations using Spice tools are typically performed. Such tools rely on static compact models describing the behavior of the individual circuit components such as transistors. In reality, the behavior of the transistors changes over time due to aging, for instance, as a consequence of bias temperature instabilities (BTI). BTI is typically referred to as a drift of the threshold voltage of a transistor due to charge trapping at oxide and interface defects. To explain BTI, power-law-like mathematical expressions are often employed. However, using these simple formulas, the experimental data can only be replicated with limited accuracy. To evaluate the performance of logic inverter circuits made from 4H-SiC CMOS transistors with high precision, we use a physics-based defect model to describe the change of the device behavior from a defect-centric perspective. Our results indicate the limitations of using power-law-like formulas as they lead to an overly pessimistic estimation for circuit parameters.

Abstract: Silicon dioxide (SiO₂) layers deposited on 4H-SiC and subjected to different post deposition annealing (PDA) in NO and N₂O were studied to identify the key factors influencing the channel mobility and threshold voltage stability in lateral implanted 4H-SiC MOSFETs. Cyclic gate bias stress measurements allowed to separate the contributions of interface states (N_it) and near interface oxide traps (NIOTs) in the two oxides. The reduction of these traps in the NO annealed sample is due to the lower amounts of sub-stoichiometric silicon oxide (~1nm) and carbon-related defects (<1nm) at the interface, as could be demonstrated by Electron Energy Loss Spectroscopy. The experimental results indicate that limiting the SiC re-oxidation during post-deposition annealing in MOSFET technology is a key factor to improve the mobility and threshold voltage stability.

Abstract: Control of defects at or near the MOS interface is paramount for device performance optimization. The SiC MOS system is known to exhibit two types of MOS defects, defects at the SiO₂/SiC interface and defects inside of the gate oxide that can trap channel charge carriers. Differentiating these two types can be challenging. In this work, we use several electrical measurement techniques to extract and separate these two types of defects. The charge pumping method and the ultrafast pulsed I-V method are given focus, as they are independent methods for extracting the defects inside the gate oxide. Defects are extracted from low voltage n-channel MOSFETs with differently processed gate oxides: steam-treatment, dry oxidation and nitridation. Ultrafast pulsed I-V and charge pumping gives comparable results. The presented analysis of the electrical characterization methods is of use for SiC MOSFET process development.

Abstract: The electrical behaviour of irradiated and post-irradiation annealed nMOSFETs with an implanted p-type body and having a N₂O oxynitrided gate oxide is analysed in this work. This study reveals the existence of a “threshold fluence” which might change the predominant SiO₂/SiC interface charge trapping type from donors to acceptors at a given energy. The irradiation fluence and energy limit that guaranty a normal or improved operation of the MOSFETs are also given.

Abstract: The overall radiation response to X-ray exposure of metal-oxide-semiconductor (MOS) capacitors, subjected to two different post-deposition-annealing (PDA) processes in N₂O or POCl₃ atmospheres, was investigated by capacitance-voltage (C-V) analyses. The production rate and saturation density of electrically active defects, different for the two oxides, demonstrated an additional contribution to the defects formation coming from the annealing treatements. The higher susceptibility of the POCl₃-annealed oxide respect to the N₂O annealed is discussed.

Abstract: In this work, nanocrystal nonvolatile memory devices comprising of silicon nanocrystals located in gate oxide of MOS structure, were comprehensively studied on specialized modular data acquisition setup developed for capacitance-voltage measurements. The memory window formation, memory window retention and charge relaxation experimental methods were used to study the trapping/emission processes inside the dielectric layer of MOS capacitor memory. The trapping/emission processes were studied in standard bipolar memory mode and in new unipolar memory mode, which is specific for nanocrystalline nonvolatile memory. The analysis of experimental results shown that unipolar programming mode is more favourable for nanocrystalline memory operation due to lower wearing out and higher breakdown immunity of the MOS device’s oxide. The study was performed for two types of nanocrystalline memory devices: with one and two silicon nanocrystalline 2D layers in oxide of MOS structure correspondingly. The electrostatic modelling was presented to explain the experimental results.