Papers by Keyword: Copper Interconnect

Abstract: A novel signaling technique for on-chip carbon nanotube interconnect aiming a higher bitrate in the range of Terahertz (THz) with low power dissipation, employing the current mode signal transportation is proposed in this paper. The technique exploits the combined advantages of current mode signaling and carbon nanotube. Using the equivalent circuit model, the transfer function is derived for the current mode carbon nanotube interconnect. Current mode signaling through carbon nanotube interconnect is simulated in MATLAB and HSPICE to study its efficiency and performance. The results are compared with the existing voltage mode CNT, current mode copper and optical interconnect. The proposed current mode signaling for carbon nanotube interconnect achieves 10² times lesser power delay product and 90% lesser delay than voltage mode. It exhibits lesser delay, 1000 times in local and 1.2 times in global and lesser power delay product by the factor of 1000 as compared with optical interconnect.

Abstract: The theoretical and experimental work is executed for study the impact of anneal on the grain size, electromigration (EM) reliability of copper (Cu) interconnect system, and subsequently find the optimized anneal condition. EM accelerated failure tests are carried on the Cu interconnect samples with 0.2μm line width, which are produced at different anneal conditions. It is shown that anneal can lead the grains to grow to become larger, and lessen the EM diffuse path. As a result, the EM diffuse active energy (Ea) of Cu interconnect is enhanced, and the ability against the EM of Cu interconnect is improved. By comparing the EM character of Cu interconnects produced at different anneal conditions, results can be obtained as below: the anneal time should be maintained 40 minutes at least in order to achieve fully anneal and excellent ability against the EM; the anneal temperature should be set about 350°C approximately, because high temperature (beyond 400°C) anneal can induce the other reliability issues, which will have a strong negative impact on the EM reliability. The results in this paper are significance for Cu interconnect technology optimize and are beneficial to improve the EM reliability of the Cu interconnect system.

Abstract: The thermo-creep deformation of interconnects related to the residual stress, directly affects their performance and lifetime. In this paper, we proposed an optical method to measure the residual thermo-creep deformation of copper interconnects. This method takes advantages of grating fabrication and the phase-shifting scanning electron microscope (SEM) moiré method. The residual thermo-creep deformation can be acquired through deformation transformation. A one-way grating with frequency of 5000 lines/mm is fabricated on the surface of the copper line in a focused ion-beam (FIB) system. The principal direction of the grating is along the axis of the copper line. The sample is heated in a high temperature furnace under 90 °C for 70 min. The SEM moiré patterns before and after heating are recorded by a field emission SEM in low vacuum. Through the random phase-shifting algorithm, the residual thermo-creep deformation of the copper interconnect line is found to be 500 με. The cause of the tensile strain is analyzed. This work offers an effective technique for measuring the creep deformation of the film lines.

Abstract: Electromigration(EM) failure can be occurred in the via because of the high aspect ratio of Via and the high stress in the via. The theoretical and experimental study is developed in detail. The different via structures are designed and the simulation and accelerate test is operated. The result shows the current density and electric field in the via is decreased apparently and reliability is improved by use the structures, so it is considered of the practical means for improving the copper via interconnect reliability. Finally, two optimized via structures are advanced based on the result of experiments and simulations. The two structures are instructive for the design and manufacture.

Abstract: Vapor-, electro-, and electroless-deposits have usually strong fiber textures. When annealed, the deposits undergo recrystallization or abnormal grain growth to reduce their energy stored during deposition. The driving force for recrystallization is mainly caused by dislocations, whereas that for abnormal grain growth is due to the grain boundary, surface, interface, and strain energies. During recrystallization and abnormal grain growth, the texture change can take place. The recrystallization and abnormal grain growth textures are in general of fiber type. However, copper interconnects are subjected to non-planar stress state due to geometric constraints during room temperature and/or elevated temperature annealing. The annealing textures of the thin films and copper interconnects are discussed in terms of the minimization of the surface, interface, and strain energies, the grain boundary energy and mobility, and the strain-energy-release maximization.