Papers by Keyword: Current Gain

Abstract: Bipolar silicon carbide devices are attractive for high power applications offering high voltage devices with low on-state voltages due to plasma flooding. Unfortunately, these devices suffer from bipolar degradation, which causes a significant degradation of the on-state voltage. To explore the generation of stacking faults, which cause the degradation, the impact of the current density and temperature on bipolar degradation is investigated in this work. The analysis is done by stressing the base-collector diode of 1.2 kV bipolar junction transistors (BJTs) as well as the BJTs in common-emitter mode operation with different current densities at different temperatures.

Abstract: This paper proposes a novel high-gain 4H-SiC BJT structure with a p-type epitaxial layer on top of the extrinsic base layer. The current gain of the novel structure is improved by 140% compared with the conventional one by the simulator tool with the number of reasonable interface traps, which could be ascribed to the epitaxial layer to reduce the surface recombination in the extrinsic base. The process to fabricate this structure is also proposed in the paper.

Abstract: The current gain stability of a second generation of 1200 V rated SiC Junction Transistors (SJTs) under long-term DC and pulsed current operation is investigated. A 1000-hour long, 200 A/cm² DC current stress results in a ≈ 10% reduction of the current gain (β) during the early stages of the stress test, while the β is perfectly stable for the remainder (>90%) of the stress duration. The same amount of stress charge applied as a pulsed current in lieu of DC current results in similar extent of β degradation for the Gen-II SJTs. The pulsed current stressing is conducted at frequencies ranging from 50 kHz to 200 kHz, at a fixed duty cycle of 0.5.

Abstract: Short-circuit (SC) robustness of 1200 V-rated SiC npn Junction Transistors (SJTs) and commercial power DMOSFETs is investigated. Due to low (2x) overdrive base currents and low short-circuit currents, SJTs demonstrate superior SC capability including: (a) minimum short-circuit withstand time (t_SC) of 14 µs, even at V_DS=1000 V (b) Perfectly stable output and blocking characteristics after 10,000, 10 µs long SC pulses at 800 V, (c) t_SC ≥ 18 µs at 800 V up to (at-least) 175°C base-plate temperatures. In contrast, commercial (Gen-II) 1200 V/80 mΩ SiC MOSFETs exhibit catastrophic failure beyond t_SC = 7 µs at 500 V, and t_SC = 3 µs at 800 V, due to excessive SC currents of > 200 A resulting in junction temperatures in excess of 650°C. The MOSFET’s drain leakage current increases by a factor of 120, and the V_TH reduces by 20%, after 7 µs-long SC pulses at 500 V.

Abstract: The influence of varying the emitter-base geometry, i.e., the emitter width (W_E), emitter contact–emitter edge distance (W_n), and base contact–emitter edge (W_p) on the on-state characteristics in 5.6 kV implantation free 4H-SiC BJTs are investigated. The BJTs present a clear emitter size effect pointing out that surface recombination has a significant influence on current gain (β). The results show that the influence of varying W_p on the β is higher than W_n. A distance of 3 μm between emitter contact and base contact to the emitter edge (W_n = W_p = 3 μm) is the optimized value to have a BJT with a high β, and low on-resistance (R_ON) at a given W_E.

Abstract: SiC Junction Transistors (SJTs) with 1900 V Drain-Source breakdown voltages, current gain (h_FE) higher than 120 and low on-resistance of 22 mΩ (3.5 mΩ-cm²) are reported in this paper. SJTs with a pre-stress h_FE of 90 suffer only a 10% reduction of the h_FE after 190 hours under a 200 A/cm² DC current stress at a T_J of 125°C, while a similar stress on earlier generation SJTs resulted in over 25% h_FE reduction in only 25 hours. SJT die with pre-stress h_FE in the range of 120-125 show absolutely no current gain degradation even after a 300°C/ 2 hour stress at 60 A/cm² DC drain current.

Abstract: SiC npn Junction Transistors (SJTs) with current gains as high as 132, low on-resistance of 4 mΩ-cm², and minimal emitter-size effect are demonstrated with blocking voltages > 600 V. 2400 V-class SJTs feature blocking voltages as high as 2700 V combined with on-resistance as low as 5.5 mΩ-cm². A significant improvement in the current gain stability under long-term high current stress is achieved for the SJTs fabricated by the high gain process.

Abstract: In this work, large area SiC BJTs with good long-term stability in 1000 hrs DC stress tests are demonstrated. It is also illustrated how wafer scanning techniques can be used to reject BJT dies with basal plane dislocations, thereby eliminating the risk for bipolar degradation.

Abstract: Performance of 4H-SiC BJTs fabricated on a single 100mm wafer with different SiC etching and sacrificial oxidation procedures is compared in terms of peak current gain in relation to base intrinsic sheet resistance. The best performance was achieved when device mesas were defined by inductively coupled plasma etching and a dry sacrificial oxide was grown at 1100 °C.

Abstract: Inductive coupled power transfer system is based on the principle of electromagnetic induction to transfer power from the primary side to the secondary side of a loosely coupled transformer, which can transfer electricity wirelessly. The loosely coupled transformer has large leakage inductance, which reduces the power transfer efficiency. In order to reduce the leakage inductance, a capacitance is used at the primary side and secondary side of a loosely coupled transformer, which can increase the power transfer efficiency. For four different compensation structures, this paper analyses the coupling coefficient and the secondary quality factor’s influence on the voltage gain, current gain and transfer efficiency, and also compares different compensation structures