Papers by Keyword: Defect

Abstract: Diamond is nominated as a material candidate for future high power device due to its superior material properties and resulting very high FOM. In this paper, our recent progresses and the expected possibilities of diamond for power electronics applications are introduced as short review. Firstly for the epitaxial growth, by adopting step-flow epitaxial growth by off- angle substrate with optimized growth conditions, we have succeeded in reducing these killer defects almost six orders from 106cm-2 to almost 100cm-2 levels. For the substrate, our recently developed technology to fabricate diamond plates from bulk, 12x13mm2 size are available to use, that can avoid fabrication difficulties with small size substrate. Secondly for the device, primitive studies showed possibly for the advantage of diamond such as low reverse leakage current, high temperature and high current density operation.

Abstract: 4H-SiC single photon avalanche diodes are reported. A separate absorption and multiplication non-reach through device structure was optimized for operation in Geiger mode. An estimated dark current at a gain of 1000 was ranging between 0.4 pA (0.75 nA/cm2) and 20nA (38 A/cm2) on devices with an effective mesa diameter of 260 m. The electron beam induced current technique was used to image defects in the active region of studied devices. Increased reverse bias leakage current and increased Geiger mode dark count probability were correlated with the presence of large number of defects. Single photon detection efficiencies of up to 11% were measured at a wavelength of 266 nm in Geiger mode.

Abstract: Defect formation during the ion implantation/annealing process in 4H-SiC epilayers is investigated by synchrotron reflection X-ray topography. The 4H-SiC epilayers are subjected to an activation annealing process after Aluminum ions being implanted in the epilayers. The formation modes of extended defects induced by the implantation/annealing process are classified into the migration of preexisting dislocations and the generation of new dislocations/stacking faults. The migration of preexisting basal plane dislocations (BPDs) takes place corresponding to the ion implantation interface or the epilayer/substrate interface. The generation of new dislocations/stacking faults is confirmed as the formation of Shockley faults near the surface of the epilayer and BPD half-loops in the epilayer.

Abstract: Silicon carbide (SiC) could be a good candidate for Diluted Magnetic Semiconductor (DMS). In this paper we report on preliminary results on the microstructure of Fe-implanted 6H-SiC subsequently submitted to Rapid Thermal Annealing (RTA), laser processing in the solid phase and swift heavy ion irradiation and analyzed by means of X-ray diffraction (XRD) and Rutherford backscattering and channeling (RBS/C).

Abstract: 4H Silicon Carbide (4H-SiC) has a great potential for low-loss power devices due to its superior electrical properties. However, the increase in demand for the power devices requires high quality SiC substrates and epitaxial layers. Mercury probe Capacitance Voltage (Hg CV) measurement is a well known procedure to characterize epi layers grown on SiC substrates, due to its non-destructive technique. However, careful calibration of the tool is very important for repeatable and accurate measurements. Here we present very close repeatability of Hg CV within 2.4% (standard deviation 0.7%), between different Solid State Measurements (SSM) setups compared with Ni Schottky (NiS) CV. In addition to growing uniformly doped epi layers, high surface quality of the epi layer is also needed for improved device performance. Improved process conditions resulted in a smooth epi with a surface roughness Ra 1.2 nm for a 6 µm thick epi layer. Molten Potassium Hydroxide (KOH) etching analysis also revealed a significant correlation between the surface roughness and epi defects.

Abstract: An attempt is made, in the light of recent developments in the identification of intrinsic defects in 4H SiC, to account for differences that have been reported after electron-irradiation of different samples and to discuss the progression of defects that is observed on annealing. The emphasis is placed on internal stress in the material and on defects involving carbon anti-sites and silicon vacancies because they are readily detected by photoluminescence.

Abstract: 1 MeV ion implantations of 4H SiC have been performed to various doses with ion probes of 5 µm diameter. Defect introduction has been studied by microscopic photoluminescence.

Abstract: As-grown and 116 keV electron-irradiated n-type 3C and 4H-SiC epilayers were electrically characterized by means of Fourier-transform deep level transient spectroscopy (FT-DLTS). A total of four deep levels, in the 0.20-0.73 eV range, below the conduction band, have been detected. By considering the band gap offset between 4H and 3C polytypes, we found that the deepest level in 3C-SiC labeled K3 (Ec-0.73 eV) has an energy position close to the EH6/7 level in 4H-SiC. An electron-dose dependence study of K3 and EH6/7, reveals that these two centers display a similar dose dependence behavior, suggesting that they may be related to the same defect.

Abstract: Availability of high-quality, large diameter SiC wafers in quantity has bolstered the commercial application of and interest in both SiC- and nitride-based device technologies. Successful development of SiC devices requires low defect densities, which have been achieved only through significant advances in substrate and epitaxial layer quality. Cree has established viable materials technologies to attain these qualities on production wafers and further developments are imminent. Zero micropipe (ZMP) 100 mm 4HN-SiC substrates are commercially available and 1c dislocations densities were reduced to values as low as 175 cm-2. On these low defect substrates we have achieved repeatable production of thick epitaxial layers with defect densities of less than 1 cm-2 and as low as 0.2 cm-2. These accomplishments rely on precise monitoring of both material and manufacturing induced defects. Selective etch techniques and an optical surface analyzer is used to inspect these defects on our wafers. Results were verified by optical microscopy and x-ray topography.

Abstract: In semiconductor processing, test wafers are used as particle monitors, film thickness monitors for deposition and oxide growth measurements, dry/wet etch rate monitors, CMP monitors, as well as characterizing new and existing equipment and processes. Depending on fab size and capacity, monthly test wafer usage can be tens of thousands or more. Due to the ever increasing demand for silicon between the IC and solar markets and the high cost of 300mm wafers, chip manufacturers are increasing their efforts to reduce overall spending on silicon - currently by far the largest non equipment related cost [1]. One approach taken by many chip makers is the concept of extending the usable life of test wafers by re-using them as many times as possible through a reclaim process.