Papers by Keyword: Device Process

Abstract: Learning by the actual experience of fabrication and evaluation of a p-n junction is a very effective way for students to obtain a deep meaningful understanding of the fundamentals of semiconductor physics. To achieve this requirement at a real-world classroom situation, a simplified fabrication process for making the silicon p-n junction as the educational application was studied. The process without using the lithography process, and in use of simple thermal diffusion furnace under the air environment for the impurity thermal diffusion process by using phosphorous silicate glass (PSG) thin film prepared by the Sol-Gel material as the phosphorus (P) diffusion source was proposed and tested. As the results, it was obtained that the impurity concentration and diffusion depth were controlled well by this method, and good rectification phenomenon of the p-n junction was successfully observed. The typical diode factor n of the p-n junction was approximately 2.3. The p-n junction also performed well as a solar cell. The FF is approximately 0.7. These results show that it is possible to use the p-n junction prepared by this simplified process as the educational device to help students’ understanding of the theory of the p-n junction.

Abstract: Condition dependences of defect formation in 4H-SiC epilayer induced by the implantation/annealing process were investigated using synchrotron reflection X-ray topography and transmission electron microscopy. Nitrogen, phosphorus or aluminum ions were implanted in the 4H-SiC epilayers and then activation annealing was performed. To compare the implantation/annealing process, a sample receiving only the annealing treatment without the implantation was also performed. Two different crucibles (conventional and improved) were used in the annealing process. The formation of single layer Shockley-type stacking faults near the surface was found to have no ion-implantation condition or crucible dependence. The formation of BPD half-loops and the glide of pre-existing BPDs showed clear dependence on the crucibles.

Abstract: Defect formation during the ion implantation/annealing process in 4H-SiC epilayers is investigated by synchrotron reflection X-ray topography. The 4H-SiC epilayers are subjected to an activation annealing process after Aluminum ions being implanted in the epilayers. The formation modes of extended defects induced by the implantation/annealing process are classified into the migration of preexisting dislocations and the generation of new dislocations/stacking faults. The migration of preexisting basal plane dislocations (BPDs) takes place corresponding to the ion implantation interface or the epilayer/substrate interface. The generation of new dislocations/stacking faults is confirmed as the formation of Shockley faults near the surface of the epilayer and BPD half-loops in the epilayer.

Abstract: Defect formation during the ion-implantation/annealing process in 4H-SiC epilayers is investigated by X-ray topography, KOH etching analysis and transmission electron microscopy. Nitrogen and phosphorus ions are implanted in the 4H-SiC epilayers and then activation annealing is performed at 1670 °C. Linearly arrayed or clustered extended defects are found to be formed during the implantation/annealing process by comparing X-ray topography images taken before and after the process. It is confirmed that the defect arrays are formed underneath a shallow groove on the surface and consist of a high density of basal-plane Shockley-type stacking faults.

Abstract: Technological aspects of ion implantation in SiC device processes are described. Annealing techniques to suppress surface roughening of implanted SiC (0001) are demonstrated. Trials to achieve a low sheet resistance are described for n-type and p-type doping. Implantation into the (11-20) face is also presented. Electrical behaviors of implants near implanted tail regions are discussed based on experiments.