Papers by Keyword: Device Simulation

Abstract: This paper presents for the first time a comparison between experimental measurements of Optical Beam Induced Current (OBIC) and finite element simulations on high-voltage bipolar diodes. Two peripheral protection structures were chosen: a simple MESA protection and a MESA + JTE combination. Comparable experimental and simulated results were obtained in both cases.

Abstract: A 1.2 kV lateral RESURF Schottky diode (TZ-SBD) have been designed from SZ-SBD that can recover from a single-event effect (SEE) in which a heavy ion traverses the device at a linear energy transfer (LET) of 60 MeV·cm²/mg, ESA’s standard. Compared to SZ-SBD, TZ-SBD has an additional split in the N-drift region which is usually used to improve the electric field distribution so its breakdown voltage is improved by 9%. During the single events simulations, the maximum temperature is 919 K with reverse voltage (VR) = 1200 V and LET = 60 MeV·cm²/mg, which is much lower then the SiC melting temperature (3100 K) and the chemically unstable temperature of SiC in the presence of metal (1073 K).

Abstract: It has recently been shown that interface defect density (D_it) at SiO₂/SiC interfaces can have non-uniform clustered distribution through the measurement by local deep level transient spectroscopy (local DLTS). Here we investigate the influence of the non-uniform D_it clustering on the field-effect mobility in SiC metal-oxide-semiconductor field effect transistors (MOSFETs) by device simulation. We develop a three dimensional numerical model of a SiC MOSFET, which can incorporate actual D_it distributions measured by local DLTS. Our main result is that the impact of the non-uniform D_it clustering on field-effect mobility is negligible for a SiC MOSFET with high D_it formed by dry thermal oxidation but it becomes significant for that with lower D_it by post-oxidation annealing. The result indicates that channel mobility can be further improved by making D_it distribution uniform as well as reducing D_it.

Abstract: Expansion of single Shockley stacking faults (SSFs) during forward current operation is an important issue, because it decreases the reliability of 4H-SiC bipolar devices. In this paper, we propose a method for analyzing SSF dynamics based on free energy under current conduction, temperature, and resolved shear stress conditions. The driving force for dislocation dissociation reactions and formation of SSFs is incorporated into the free energy function, including chemical potential, stacking fault energy, crystallographic energy, gradient energy and elastic strain energy. The net energy gain of the chemical potential was calculated as a function of temperature and current conduction through use of the a TCAD device simulator based on the Boltzmann equation, Poisson equation and the current continuity equation concerning electron and hole distributions with self-consistency. It was confirmed that SSF dynamics can be simulated by the proposed method. It was also found that SSF formation can be attributed to quantum well variation in which electrons in n-type 4H–SiC enter SSF-induced quantum well states to lower the energy of the dislocation system.

Abstract: The electrical properties of bottom-gate amorphous InSnZnO (a-ITZO) thin-film transistors (TFTs) with different channel thicknesses (TITZO) were investigated. The difference between front- and back-channel interface traps influence on subthreshold swing (S) and turn on voltage (Von) of a-ITZO TFTs was further analyzed using device simulation. Variations of front-channel interface traps (Naf) on S and Von were hardly dependent on TITZO. However, variations of S and Von became larger for thinner TITZO TFT when back-channel interface traps (Nabk) varied; which can be explained by considering screening length. Not only Naf but also Nabk are important factors of S and Von to achieve high performance thinner oxide TFT.

Abstract: In this paper, the static and dynamic characteristics of a 1200 V and 120 A silicon carbide (SiC) MOSFET power module has been measured, simulated and verified in the PSpice circuit simulation platform. Experimental measurements and PSpice simulations are performed to extract the technology dependent modeling parameters. The model is implemented in the PSpice circuit simulation platform using both standard components and analog behavior modeling (ABM) blocks. The simulation results of the model is fairly accurate and correlates well with the measured results over a wide temperature range. The developed model is used to facilitate converter design at cell level and hence predict and optimize the cell performance (i.e., energy losses) with varying circuit parameters (e.g., stray inductances, temperatures, gate resistances etc.,).

Abstract: The characteristics of a 1200 V and 800 A bipolar junction transistor (BJT) power module has been measured, simulated and verified for the first time in the PSPICE platform. The simulation model is based on a silicon carbide (SiC) Gummel-Poon model for high power applications. The implemented model has been extended with temperature dependent equations in order to extend the BJT operating temperature range. PSPICE simulations are performed to extract technology dependent modeling parameters coupled with static and dynamic characteristics of BJTs at different temperatures and validated against the measured data. The performance of the SiC BJT model is fairly accurate and correlates well with the measured results over a wide temperature range.

Abstract: The simulator of power part of electric drive for research purposes of electric drives is under consideration in the paper. It is based on the software and hardware of National Instruments Company and includes mathematical model of converter, motor and load. The simulator is designed to setting up the electric drive and to explore the modes of its operation.

Abstract: Ultrahigh-voltage SiC PiN diodes with an original junction termination extension (JTE) structure and improved forward characteristics are presented. A space-modulated JTE (SM-JTE) structure was designed by device simulation, and a high breakdown voltage of 26.9 kV was achieved by using a 270 μm-thick epilayer and 1050 μm-long JTE. In addition, lifetime enhancement process via thermal oxidation was performed to improve the forward characteristics. The on-resistance of the SiC PiN diodes was remarkably reduced by lifetime enhancement process. The temperature dependence of the on-resistance was also discussed.

Abstract: This paper addresses the design diagnostic study of 4H-SiC based IGBTs using two dimensional numerical computer simulations. Using identical set of physical device parameters (doping, thicknesses), simulated structure was first calibrated with the experimental data. A minority carrier life time in the drift layer of 1.0 1.6 μs and contact resistivity of 0.5 - 1.0 x 10^-4 Ω-cm² produces a close match with the experimental device. A decay in the device transconductance and threshold voltage is observed with increasing temperature. The on-resistance first decays with temperature (i.e., increased in ionization level, and increase in minority carrier life time), stays nearly constant with further increase in the temperature (may be all carriers are now fully ionized and increase in carrier life time is compensated with decrease in the carrier mobility) and finally increases linearly with temperature (> 450 K) due to decrease in the carrier mobility. The design of buffer layer is investigated that shows lower on-state losses with thin high doped buffers. For the design of devices over 15 20 kV, the design of drift layer demands a doping of < 2.0 x 10¹⁴ cm^-3 with epitaxial layer quality giving a carrier life time over 2.0 μs.