Papers by Keyword: Diode

Abstract: In this work, we investigate the static electrical parameters of 1200 V 4H-SiC power diodes with various designs and architectures (Schottky, PiN, and JBS with hexagonal or stripes anode), fabricated on two types of 150 mm substrates (single crystal 4H-SiC reference and 3C-poly silicon carbide based substrates: SmartSiC^TM). I(V) measurements are carried out in both reverse and forward modes to assess the impact of designs and substrates. Non-destructive avalanche mode is reached with similar performance (leakage, V_AV) observed for both substrates (due to identical drift layers and device structures). All diode designs on SmartSiC^TM exhibit a larger current conduction and less resistance in the ohmic regime (compared to bulk), whatever the temperature (up to 200°C). Partitioning model is also proposed for evaluating the substrate contribution on the measured specific resistance and on the observed SmartSiC^TM gains.

Abstract: Novel diode structure which looks like DMOSFETs with the gate-shorted to n⁺ source has been developed for the first time. The lateral JFET channel as a built-in channel instead of gate oxide is integrated and it is pinched-off under the zero bias condition. As JFET diode decreases the forward voltage drop using JFET channel efficiency rather than the cell pitch reduction or the increase of doping concentration in n-SiC drift region, V_F and capacitive charges which have a trade-off relationship typically could be decreased simultaneously and a better switching performance is also expected accordingly. Figure-of-Merit (=V_F×Q_C) of the proposed JFET diode has been improved by 20.2% in average compared to that of JBS diode and this FOM would be the best in class among 1200V SiC diode products.

Abstract: The avalanche robustness of 430 V SiC avalanche diodes at high temperatures is investigated. The UIS test was performed with fixed avalanche time in order to avoid the effect of a thermal diffusion time on an avalanche energy. It is found that the avalanche energies at 25 are 10.5 J/cm² for and 12.7 J/cm² for while those at 170 are 8.02 J/cm² and 9.96 J/cm², respectively. Their temperature coefficients are about-0.018 J/cm²K, which are much smaller than those of typical SiC-MOSFETs, indicating that the SiC diodes maintain great avalanche robustness even at high temperatures.

Abstract: Silicon carbide (SiC) power devices such as Schottky diodes and metal-oxide semiconductor field-effect transistors (MOSFETs) are susceptible to failure by terrestrial neutron single-event burnout (SEB) while in the high-voltage blocking state. In this study the effects of the drift layer design of 650V SiC vertical power diodes and MOSFETs have been studied. TCAD simulations of different device designs have been performed, and fabricated device single-event burnout (SEB) properties are compared between the devices fabricated. We find that the standard 650V devices have a low area-scaled failure-in-time (FIT/cm²) such that essentially no failures (0.01 FIT/cm²) are expected at 400V drain-source bias (V_DS) operation and below. An improved design allows the SEB failure rate curve to be shifted downward in failure rate, such that at for a given V_DS operation condition, the FIT/cm² can be decreased by 10 - 100 times, depending on the V_DS value. This allows operation at about 75V higher V_DS value with a similar SEB failure rate, allowing these devices to be used in a wider range of applications.

Abstract: The goal of this work is to use MATLABSimulink to create a simulation of a DC-to-DC boostconverter it, utilizing SPMC topology that is a matrixconverter with only one phase. With the outputboosted more than that the fluctuations are quiet high.In this project work, we have tried to boost up theoutput to five times after keeping the fluctuations aslow as possible. The output voltage is controlled usingthe PWM approach. IGBT is used in four pairs andtaken as the switching device. Four pairs of diodes arealso used with the IGBTs and are placed in parallel andopposite direction. The simulation was performed at aswitching frequency of 10 kHz, and the findings werein excellent agreement with the quadrant operation'sfirst quadrant, and it was able to increase the voltageof itsinput by about five times . In addition, an inverterissuccessfully created, demonstrating the use of matrixtopology.

Abstract: We report successful demonstration of 2kV, SiC super-junction (SJ) PiN diodes formed by deep implantation of Al and N. In our devices, alternating 12μm deep n-type and p-type SJ pillars fabricated on a 10μm pitch and result in a SJ diode with a measured blocking voltage 500V higher than comparable non-SJ diodes. Four activation anneals ranging from 1700 °C to 2000 °C were compared for effectiveness in eliminating post-implant lattice damage, and the optimum anneal condition was identified.

Abstract: Designed for 6500V 4H-SiC JBS diodes, a highly-efficient termination structure of a non-uniform multiple floating field limiting rings (MFFLR) featuring with a non-uniform ring spacing and a multiple region division is studied and purposed. For each region, ring spacing is modulated independently by a multiplication factor and a linear increment factor. The non-uniform MFFLR structure is simulated and optimized for a better electric field distribution and a higher breakdown voltage. Based on the simulation results, 4H-SiC JBS diodes with the optimized non-uniform termination designs are fabricated. Experimental results show that the SiC JBS diode with optimized non-uniform MFFLR termination structure can achieve a breakdown voltage of up to 7800 V, and its termination efficiency is about 94% of an ideal parallel-plane junction’s. Our results demonstrate that the optimized non-uniform MFFLR termination structure is capable for SiC JBS diodes with breakdown voltage of 6500V and above. Our results can provide a valuable design methodology of edge termination structures for other high-voltage SiC devices.

Abstract: The effect of the field oxidation process on the electrical characteristics of 6500V 4H-SiC JBS diodes is studied. The oxide thickness and field plate length have an effect on the reverse breakdown voltage of the SiC JBS diode. According the simulation results, we choose the optimal thickness of the oxide layer and field plate length of the SiC JBS diode. Two different field oxide deposition processes, which are plasma enhanced chemical vapor deposition (PECVD) and low pressure chemical vapor deposition (LPCVD), are compared in our paper. When the reverse voltage is 6600V, the reverse leakage current of SiC JBS diodes with the field oxide layer obtained by LPCVD process is 0.7 μA, which is 60% lower than that of PECVD process. When the forward current is 25 A, the forward voltage of SiC JBS diodes with the field oxide layer obtained by LPCVD process is 3.75 V, which is 10% higher than that of PECVD process. There should be a trade-off between the forward and reverse characteristics in the actual high power and high temperature applications.

Abstract: The triangular defect is a common defect in the 4H-SiC epitaxy, which is also one of the killer defects to the 4H-SiC devices. In this paper, the 4H-SiC epitaxial wafer was grown by chemical vapor deposition (CVD). The formation mechanism of triangular defects in silicon carbide epitaxy was analyzed, and the solutions were proposed. Then, the diodes were fabricated on the wafer, and the influence of triangular defects on the forward and reverse I-V characteristics of 4H-SiC diodes was analyzed by tracking the defects map. The results show that the presence of triangular defects can lead to the reduction of the reverse voltage by about 40%, an increase of the leakage current by four orders of magnitude, and an increase of the forward conduction resistance.

Abstract: We have studied capacitance mode Deep Level Transient Spectroscopy (DLTS) of five 4H-SiC Schottky diode and PiN diode designs. Comparing with previous DLTS studies, we have identified four traps levels, Z_1/2, EH₁, EH₃ and EH₅. Additionally, a new trap level, EH₁, is prominent in blanket Al⁺ and B⁺ high-energy implanted samples but less so in mask-implanted samples. Al⁺ implantation increases EH₃ (associated with silicon vacancy) and EH₅, while B⁺ implantation significantly reduces EH₃. The Z_1/2 peak (associated with carbon vacancy) is reduced to very low levels after B⁺ and Al⁺ implantation.