Papers by Keyword: Dislocation Conversion

Abstract: Dislocations and stacking faults in 4H-SiC (0001) _si epitaxial wafer was inspected by mirror projection electron microscopy (MPJ) with the aid of low-energy SEM and FIB-STEM. MPJ observation found dislocation conversion near the wafer surface, and the conversion was confirmed by micro etch pit and low energy SEM method. Another conversion occurred in the epitaxial layer on array of TED half loops, which were detected by MPJ, was also observed by cross-sectional STEM.

Abstract: Two types of shallow surface defects associated with treading dislocation were found out by using mirror projection electron microscope. One was single groove with a dimension of about 4 nm in depth, 2 μm in width and 15 μm in length, named “as nanogroove”. The other was a shallow groove at 1.3nm in depth being between pair of hillocks at 2-3 nm in height and 1.5 μm in distance, named as “nanohillock pair”. Dislocations combined with the defects were found out by micro-KOH etching method with low-energy scanning electron microscopy. The dislocations were identified by g-b analysis using scanning transmission electron microscopy as threading edge dislocations converted from basal plane dislocation at bulk-epi layer interface or within epi layer.

Abstract: We detail a comprehensive approach to preparing epiwafers for bipolar SiC power devices which entails etching the substrate, growing a semi-sacrificial basal plane dislocation (BPD) conversion epilayer, polishing away a portion of that conversion epilayer to recover a smooth surface and then growing the device epilayers following specific methods to prevent the reintroduction of BPDs. With our best processing, we achieve a BPD density of < 10 cm-2 and an extended defect density of < 1.5 cm-2. Specifics of low BPD processing and particular concerns and metrics will be discussed in regard to process optimization and simplification.

Abstract: Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to <10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The first low BPD technique employs a selective etch of the substrate prior to epilayer growth to create a near on-axis surface where BPDs intersect the substrate surface. The second low BPD technique employs lithographic and dry etch patterning of the substrate prior to epilayer growth. Both processes impede the propagation of BPDs into epilayers by preferentially converting BPDs into threading edge dislocations (TEDs) during the initial stages of epilayer growth. With these techniques, we routinely achieve Vf stability yields of up to 90% in devices with active areas from 0.006 to 1 cm2, implying that the utility of the processes is not limited by device size.