Papers by Keyword: Dry Etching

Abstract: This work presents the results of process development for trench formation in SiC power devices to increase the trench depth by improving SiC/SiO₂-selectivity of the dry etch process. Motivation behind this development is to further improve the electrical properties of conventional devices like SiC MOSFETs by implementing a trench geometry, allowing the cell pitch to be increased, leading to a reduced on-resistance of SiC TrenchMOS devices. Trench etching was performed on 4H-SiC substrates by utilizing an oxide hard mask, patterned by photolithography and dry etching. The SiC trench profile was analyzed by cross-section preparation via FIB and SEM imaging. The highest SiC/SiO₂-selectivity achieved was 7.9, with SiF₄ gas flow being the most decisive parameter for it. With that, the selectivity of the standard SiC trench etch process was increased by nearly five times. SiC trenches with depths of 5 µm could be demonstrated. However, then the structural fidelity was deteriorated, with micro-trenching and sidewall bowing being the largest limitations regarding applicable trench depth in SiC power devices.

Abstract: Etching active area by dry etching method can precisely control the length and width of the devices, but it may damage the SiC surface. In this paper, we fabricated metal-oxide-semiconductor capacitors (MOSC) using different etching methods to compare the effect of etching methods on the SiO₂/SiC interface and dielectric breakdown. It is observed that dry etching will degrade the surface roughness of SiC and the interface state density at the SiO₂/SiC interface. Post-oxidation NO annealing cannot passivate the interface effectively. The breakdown field of gate oxide on the dry etched sample is also degraded. These results indicate that dry etching of SiC surface should be avoided when fabricating MOS devices.

Abstract: Effects of CF₄ etching on 4H-SiC MOS capacitor were investigated. Fluorine atoms were introduced to surface of 4H-SiC using CF₄ dry etching process as a surface treatment, and 4H-SiC MOS capacitors with dry-oxide were fabricated with this treatment. As the results, breakdown electric field of the MOS capacitors was increased and variation of the characteristics became lower than that of MOS capacitor without this treatment.

Abstract: In this work, we present a planarization concept for epitaxial SiC trench structures involving reactive ion etching (RIE) and inductive coupled plasma (ICP) dry etching. The general idea is to transfer the flat surface from spun-on BCB/photo-resist layers to deposited silicon dioxide and finally to bulk SiC by applying process conditions with the same etch rate for the different materials. In this way several microns of unwanted material can be removed and planar SiC surfaces are obtained. With this method trench structures filled by epitaxial re-growth can be planarized with smooth surfaces and good homogeneity over the wafer. Cost-efficient device manufacturing can be achieved by using standard semiconductor process equipment. This technology makes it possible to manufacture advanced epitaxial SiC material structures for devices such as trench JBS diodes and double-gate trench JFETs.

Abstract: TSV is a new technology to make interconnections between chips by creating vertical wafer-to-wafer vias. The application of ICP ( inductively coupled plasma ) dry etching to make TSV is discussed in this paper. Starting with hardware conditions of the equipment, a large number of experiments were conducted to test the process parameters combining with the fundamentals of dry etching. By constantly modifying the parameters to optimize the process, a final result of TSV with the width of 2.62um, depth of 63.5um, verticality of 89.8°and scallop of 70.3nm was realized in this paper.

Abstract: Polyimide is often used as a sacrificial layer material to make floating structure. Polyimide is also divided into photosensitive and non-photosensitive type; photosensitive polyimide currently has more negative photoresist and poor performance in many ways. Compared with photosensitive polyimide, the non-photosensitive type has low stress, stable performance and other advantages, so non-photosensitive polyimide has been chosen as a sacrificial layer material. To achieve the graphical function and release sacrificial layer, A deeply research was made in this dissertation makes on wet etching and dry etching. By controlling the wet etching process of prebake condition, exposure and developing time, and oxygen dry etching process of etching power, bias voltage and other key process parameters, a good sacrificial layer graph and etching effect have been got. Finally, it can be concluded that when the prebake conditions for 105°C, 8min and times of exposure and developing were 11s and 29s, the non-photosensitive polyimide wet etching effect is the best; when the etching power is 1000w, an oxygen flux rate is 50sccm, the reaction pressure is 30mTorr, the bias voltage is 140v, oxygen dry etching has a good effect.

Abstract: Becoming another key technology for system integration, GaAs based millimeter wave antenna is fabricated by MEMS technology, with high permittivity dielectric substrates. To obtain good performance, it is necessary to achieve the equivalent of low dielectric constant of the local area below microstrip patch antenna. The article describes deep etching fabrication and multiple etching with thick photoresist masking to creat air cavity under the microstrip patch which usually has the height from 70% to 80% of the original media substrate, thus it forms the air-mixed media substrate. Especially for precision control of the substrate thickness, use back thinning and high-precision polishing processes. At last realize back cavity depth of 227μm in the GaAs substrate and complete the process of Ka band MEMS patch antenna. The measurement results: the center frequency is 37.9 GHz, bandwidth is 4.4%, radiation efficiency above 50%.

Abstract: A new automatic RIE etching system has been developed. Multi-layers of magnetic materials were fabricated using this system. We compared the process of using conventional Ar gas plasma and the process using CO/NH₃ gas plasma. Then by combining the two processes, we achieved smooth surface and good uniformity with a good selectivity to photoresist mask. And few of corrosions appeared at the sidewall of trench. Additionally, the etching process could stop exactly at the stop layer. The whole processes ran at a chamber without control of temperature, pressure and end point detection.

Abstract: Dry etching of Pt/Ti film was carried out using Cl₂/Ar plasmas in an inductively coupled plasma (ICP) reactor. The influence of the various process parameters, such as RIE power, ICP power and Cl₂/Ar gas mixing ratio, on the etch rate and selectivity of photoresist to Pt/Ti film were investigated systematically and optimized. It was revealed that the etch rate and the selectivity strongly depended on the key process parameters. The etch rate was found to increase dramatically with increasing of RIE power and ICP power. But by changing the ratio of Cl₂ to the total gas, the maximum etch rate could be obtained at the proper ratio of 20%. The results also indicated too low or too high RIE power and the Cl₂ ratio was detrimental to the selectivity. The optimized parameters of Pt/Ti dry etching for high etch rate and low selectivity of photoresist to Pt/Ti were obtained to be pressure: 10mT, RF power: 250W, ICP power: 0W, Cl₂: 8sccm (standard cubic centimeters per minute), Ar: 32sccm.

Abstract: Silicon nano pin arrays with heights of 1.3-3.66um and diameter of 315-899nm, are fabricated by CsCl self-assemble for CsCl nano islands for mask and ICP etching for silicon pins. CsCl film is firstly deposited on the wafer by thermal evaporation and putted in the humid controlled environment to be developed to the CsCl islands with diameter of 341-915 nm as self-assembled technology. Then the ICP etching with SF6, CCl4, He gas is introduced to make the silicon nano pin by the mask of CsCl nano islands, and the silicon nano pins with the different height of 1.3-3.66 um are finished for field emission. The gated FEA templates are fabricated by photolithography process and the lift-off technology with Ti-Si film as the gate electrodes. The final template for field emission has the silicon nano pins with diameters of 31.7 nm on top, Ti-Ag film with thickness of 105nm and gate holes of 30um in diameter, and SU8 resist insulator structure with thickness of 4um and holes of 10um in diameter. The optimization of the fabrication process and the performance for the configuration will be made.