Papers by Keyword: Electrical Characterization

Abstract: In this work, the electrical properties of Mo₂C/4H-SiC Schottky contacts were studied at different annealing temperatures. In particular, the Schottky barrier height was derived by current-voltage measurements on as-deposited and 400 °C and 700 °C-annealed contacts. The Schottky barrier height was comparable for the as-deposited and 400°C-annealed Mo₂C/4H-SiC contact (0.94 and 0.96 eV, respectively), while it increased (1.07 eV) for the 700 °C-annealed Mo₂C/4H-SiC one. For the sample annealed at 700°C, the electrical characterization of the diodes was combined with the study of the surface and interface electrical properties, by Kelvin-probe force microscopy (KPFM) and frequency dependent capacitance-voltage measurements (C-f-V) and discussed assuming a Mo/4H-SiC Schottky contact (F_B =1.39 eV) as a reference. The KPFM measurements revealed a similar value of the surface potential, thus suggesting that the work function of the metal is the same in both cases. On the other hand, a higher density of interface state was obtained by C-f-V for the Mo₂C/4H-SiC system. This latter can explain the reduction of the Schottky barrier height observed for this system.

Abstract: In this work, we investigated the electrical properties evolution of Mo/4H-SiC Schottky contacts following thermal annealing treatments at temperature up to 950 °C. The electrical characterization under forward and reverse bias revealed a reduction of the barrier height from 1.45 eV (as-deposited contact) to 1.30 eV (950°C-annealed contact), with the presence of inhomogeneity in the contact, while the leakage current followed a thermionic-field emission (TFE) model after annealing at 750 °C and presented a significant increase for the 950°C-annealed contact. The electrical characterization was associated with microstructural analyses, which highlighted an enlargement of the grains forming the structure of the Mo-film and the presence of voids near the Mo/4H-SiC interface. These observations can be at the base of the variation in the electrical behavior of the contact.

Abstract: In this paper, the static and dynamic characterization of a High Voltage (10kV) 4H-SiC Bipolar Junction Transistor (BJT) is presented. Using a high-voltage source in vacuum conditions, a breakdown voltage of 11 kV was measured. Results showed that both large and small BJTs exhibit similar on-state resistance per unit area and collector current density of 55 A.cm^-2. The current gain increases with a decrease in temperature, indicating reduced charge carrier recombination at lower thermal energies. Also, BJT have been characterized in switching mode at 1 kV. The study concludes that 4H-SiC BJT demonstrates promising electrical performance for high-efficiency applications in harsh environments.

Abstract: This research focuses on developing a p-ZnO/n-ITO heterojunction diode fabricated using a low-cost, solution-based dip-coating technique. Zinc oxide (ZnO) is a wide bandgap semiconductor known for its remarkable optical and electrical properties, making it widely applicable in optoelectronic devices. This study involves the synthesis of p-type ZnO (p-ZnO) nanorods using a solution-based method and their integration with indium tin oxide (ITO) substrates to create a diode with improved rectification properties. The fabricated diode demonstrates rectification ratios of 139 in the dark and 225 under UV illumination alongside a high built-in voltage of 1.1 V. Electrical analyses were performed, including current-voltage (I-V), Hall effect, and capacitance-voltage (C-V) measurements, revealing the diode’s strong UV sensitivity, excellent photo response, and stability in extreme conditions. These characteristics position the p-ZnO/n-ITO heterojunction as a promising candidate for UV sensors and high-performance semiconductor devices in harsh environments. Future research could focus on enhancing doping strategies and exploring the integration of these diodes into flexible electronics to expand their applications in optoelectronics.

Abstract: SiC-on-Insulator (SiCOI) structures fabricated using the Smart Cut™ technique can be of great interest in order to probe the properties of a silicon carbide (SiC) transferred layer, by electrically insulating it from the receiver substrate. In this study, we report the fabrication of such a SiCOI structure using a SiC receiver, as well as its electrical and TEM characterization after high temperature annealing. We highlight a decrease of the transferred layer electrical resistivity with increasing annealing temperature, due to doping reactivation and electron mobility enhancement. After low temperature annealing (1200°C to 1400°C), deep acceptor levels, possibly located in a damaged region near the substrate’s surface, might be responsible of a non negligible electrical compensation. Beyond 1400°C however, the transferred SiC crystal is healed and electron transport is only subjected to shallow nitrogen ionization.

Abstract: In this work we report on the impact of various crystalline defects present in 4H-SiC epitaxial layers on the electrical blocking characteristics of SiC power devices. Dedicated test structures were fabricated and electrically characterized in reverse bias mode. SiC substrate and epitaxial crystal defects, as well defects due to front-end processing were detected and classified using commercial inspection tools. Devices with a single defect-type were studied which leads to a direct correlation of the leakage current spot position within the device and the obtained blocking characteristics. This gives a better understanding of each crystal defect impact on device ́s performance which leads to an improvement in the reliability and cost reduction of SiC power devices.

Abstract: We present here a study on the electrical and structural properties of p-type PbTe films doped with CaF₂. The layers were grown by molecular beam epitaxy on freshly cleaved (111) BaF₂ substrates. The doping level was monitored by the CaF₂ solid source cell temperature (T_CaF2), which varied from 500 to 1150 °C. The films with low doping level, T_CaF2 ≤ 1010 °C, exhibited flat surfaces with crystalline quality close to the undoped PbTe sample. In contrast, samples with high levels of doping (T_CaF2 > 1010 °C) presented CaF₂ agglomerates on the surface and a worse crystal quality. The hole density at 77 K versus T_CaF2 oscillated between 1.3 × 10¹⁷ and 3.6 × 10¹⁷ cm^-3 and did not exhibit a systematic behavior as the fluoride supply is raised. The results indicate that CaF₂ is not an effective p-type dopant for PbTe, due to the abscence of a resonant level close to the valence band or to compensation of extrinsic dopant levels.

Abstract: This paper aims to give an overview on some relevant aspects of the characterization of the SiO₂/4H-SiC interface, considering the properties of this system both at the interface and inside the insulator. Nanoscale scanning probe microscopy (SPM) techniques were used to get insights on the homogeneity of the SiO₂/SiC interface electrical properties upon metal-oxide-semiconductor (MOS) processing. On the other hand, capacitance and current measurements as a function of time were employed to investigate trapping states in MOS structures in the SiO₂/4H-SiC system. In particular, time-dependent gate current measurements gave information on the near interface oxide traps (NIOTs) present inside the SiO₂ layer. The impact of the observed trapping phenomena on SiO₂/SiC metal oxide semiconductor field effect transistors (MOSFETs) operation is discussed.

Abstract: In the development of SiC MOSFETs, further improvements are ongoing to improve device performances. One of the critical part at the device level is the gate oxide/semiconductor interface, being the gate oxide a standard SiO₂ layer. This work is focused on the investigation of the effect of post oxidation annealing process (POA) carried out after the deposition of high-temperature oxide (HTO) layer used for dielectric gate formation by using NO and N₂O gasses. The variation of D_it by applying the POA in N₂O is considerable with respect to the as-deposited oxide layer as the density is reduced of about two order of magnitude. A further reduction of interface trap density from 2.3×10¹⁰ to 8.5×10⁹ traps/cm² has been observed when NO POA process was applied. Full vertical power MOSFETs were also analyzed in order to measure the channel mobility of the device. Channel mobility has been seen to raise its value from 45 cm²/Vs to a value of about 62 cm²/Vs when NO-based POA process was performed. NO-based POA process results in a much more effective interface at device level.

Abstract: In this paper the Bipolar Mode Field Effect Transistor (BMFET) is demonstrated for the first time in 4H-SiC. The structure is based by two p⁺-type regions symmetrically placed at both sides of a n-type region channel and the device implements two control mechanisms: into the channel the potential barrier controls the electron flow in the off-state operations, like VJFET-based devices, whereas, during the on-state, the holes injected from the p-n junctions induce the conductivity modulation of the channel reducing the on-resistance with beneficial effects on current gain and switching operations. In order to avoid the reduction of carrier lifetime into the channel due to ion implantation and trench etching, an ad-hoc fabrication process has been set-up to enable the conductivity modulation into the channel. First experimental tests on the prototypes show the correct operations of the device as demonstrated from the changing of the output characteristic from triode-like to pentode-like behaviors, which are ascribed to the two main operation principles of the device.