Papers by Keyword: Epitaxial Growth

Abstract: The impact on doping profile, surface roughness and defect production of each process step for a suggested Multiple epitaxy and implantation (MEI) process for Super-junction has been investigated through Secondary Ion Mass Spectrometer (SIMS), Atomic Force Microscope (AFM), Deep Level Transient Spectroscope (DLTS) and Molten KOH etching. Results show that the suggested process can possibly reduce the cost of the original fabrication and speed up the process.

Abstract: This paper compares ethene and methane precursors for homoepitaxial 4H-SiC growth in planetary reactors with regards to their impact on growth rate and defectivity of the epilayers. Therefore, a comprehensive experimental study has been performed in AIXTRON G10-SiC and G5WW C planetary reactors using a standard process based on ethene and trichlorosilane precursors with conventional 150 mm n-type 4H-SiC substrates from 3 different international suppliers. Methane substituted ethene as precursor in many experiments. It was found that methane precursor can compete with ethene in terms of growth rate, epilayer thickness, and defectivity of the epilayers. By using isotopically enriched methane, Si¹²C epilayers with a ¹²C concentration of 99.96 % have been grown which can be used for SiC-based quantum technology.

Abstract: 4H-SiC is a wide-bandgap semiconductor that has become essential for power electronics due to its large bandgap, high critical electric field, and excellent thermal stability. Within the {0001} basal orientation, the two polar surfaces – Si-face and C-face – exhibit distinct behaviours during chemical vapor deposition (CVD) homoepitaxy, with direct implications for device performance and manufacturing. In this work, n-type epitaxial layers were deposited on 150 mm, 4° off-axis Si-face and C-face substrates under identical conditions in a single-wafer hot-wall LP-CVD reactor (T > 1600 °C, P = 3.0 kPa, C/Si = 1.05, silane/propane/ethylene precursors, N₂ doping, HCl additive). Characterization analysis revealed pronounced polarity-dependent differences. AFM analysis showed that C-face epilayers exhibited smoother surfaces and reduced step bunching compared with Si-face layers. Optical and photoluminescence inspections show polarity-dependent defect propagation, with the C-face displaying reduced replication of extended defects under the explored conditions. However, nitrogen incorporation on the C-face orientation was more than 25× higher than Si-face orientation and displayed poor uniformity, highlighting the limited effectiveness of site-competition epitaxy on this orientation. In contrast, the Si-face provides tighter control of doping concentration and lateral uniformity, albeit with higher step bunching and rougher surfaces. These findings emphasize a fundamental trade-off in 4H-SiC homoepitaxy: the C-face offers morphological and structural advantages, while the Si-face ensures superior doping control and process stability. A deeper understanding of these polarity-dependent mechanisms is essential to optimize epitaxial growth strategies and to enable the design of high-performance SiC power devices.

Abstract: We have demonstrated a novel process that precisely controls the wafer bow, a key parameter of overall warpage, of 4H-SiC wafers to any desired value by integrating a thermal sublimation process, Dynamic AGE-ing® (DA), immediately prior to the CVD epitaxial process. This method achieves atomic-level flatness of the CMP-finished surface independent of the growth and etching amounts, while concurrently eliminating sub-surface damage (SSD). When DA is applied to simultaneously etch the Si-face and grow the C-face, the wafer bow decreases linearly with increasing C-face growth. In wafers with poorer mechanical processing quality, an increase in bow is observed for C-face growth below 120 nm, likely due to the relaxation of SSD on that side. The process also removes SSD from the Si-face, ensuring that both sides are sufficiently cleared of damage. Furthermore, for wafers with an initially negative bow, simultaneous Si-face growth and C-face etching using DA produces a linear increase in bow. By applying these processes, we successfully adjusted the bow to –0.4 µm on an 8-inch wafer that initially measured –12.0 µm. These results indicate that, regardless of the initial bow severity, precise control of the wafer bow can be achieved without adversely affecting subsequent CVD epitaxy processes by appropriately managing the growth layer thicknesses on both faces using DA.

Abstract: Engineered SiC wafers with a thin 4H-SiC layer bonded on a polycrystalline carrier substrate for the application as substrate in epitaxy are investigated. Epitaxial layers grown on such substrates in 150 mm and 200 mm diameter are compared to those on state-of-the-art conventional substrates from different vendors. The performance of the engineered wafers is judged by doping and thickness uniformities as well as the number and statistics of killer defects in the epitaxial layer.

Abstract: This study substantiates the epigraphene formation theory on SiC, presenting it as freestanding graphene during thermal decomposition epitaxy. It was found that cool down process is responsible for the formation of the graphene buffer layer. Additionally the capping capabilities of the buffer layer have been evaluated using Raman spectroscopy and AFM measurements.

Abstract: The layer structure of 3C-SiC stacked on 4H-SiC is implemented by simultaneous lateral epitaxy (SLE). The SLE, involving spontaneous nucleation of 3C-SiC(111) on the 4H-SiC(0001) surface followed by step-controlled epitaxy, facilitates the creation of a single-domain 3C-SiC layer with an epitaxial relationship to the underlying 4H-SiC, establishing a coherent (111)//(0001) interface aligned in the basal plane. An extremely low state density at an interface between thermally grown SiO₂ and SLE-grown 3C-SiC layer is revealed by local deep level transient spectroscopy (local-DLTS) based on scanning nonlinear dielectric microscopy (SNDM).

Abstract: Solid State Detectors (SSD) are crucial for fast neutron detection and spectroscopy in tokamaks due to their solid structure, neutron-gamma discrimination, and magnetic field resistance. They provide high energy resolutions without external conversion stages, enabling compact array installations in the harsh environment of a tokamak. Research comparing diamond and 4H-SiC detectors highlights thickness as a key efficiency factor. A 250 μm SiC epilayer with low doping, grown using a high-growth-rate process, exhibits sharp interfaces and minimal defects, essential for neutron detectors. The study evaluates detector designs, and performance using a 4H-SiC substrate. Various detector designs, such as Schottky diodes and p/n diodes, are assessed via I-V and C-V measurements, addressing high depletion voltage challenges. Preliminary neutron irradiation tests validate detector functionality, energy resolution and confirming detector reliability.

Abstract: This paper presents an investigation into the surface morphology control of 4H-SiC (0001) wafers cut to 4º off during thermal processing, aiming to suppress the propagation of basal plane dislocations (BPD) into the epitaxial growth layer. Developing methods for debunching rough surfaces with macro step bunching (MSB) using thermal processes removes many of the limitations of the conventional epitaxial growth process. This study presents a surface morphology control method that includes debunching of steps by thermal sublimation etching/growth using the Dynamic AGE-ing^® (DA) method. By controlling the surface morphology before and after growth using this method, the dependence of the BPD-threading edge dislocation (TED) conversion ratio on surface morphology was systematically revealed. By selecting the optimal pre- and post-growth surface morphology, a 100 % BPD-TED conversion ratio was obtained for the 10 mm × 25 mm area. It was indicated that an innovative and stable surface morphology control technique using the DA sublimation process could solve numerous technological challenges in various fields.

Abstract: The development of non-destructive quantitative evaluation techniques for the in-plane depth distribution of sub-surface damage (SSD) layer induced by mechanical processing of chemical mechanical polishing (CMP) finished SiC wafers is essential to reduce the occurrence of crystal defects during epitaxial growth. Until now, no wafer inspection method has been able to nondestructively and quantitatively assess the in-plane depth distribution of the SSD. This study investigates the correlation between the scattered light intensity measured nondestructively by the Laser light scattering (LLS) method and the SSD depth estimated by destructive inspection using the Dynamic AGE-ing^® method, a sublimation-controlled etching and growth process, to develop a novel non-destructive SSD inspection method. As a result, it was found that there is an exponential relationship between the scattered light intensity by the LLS method on the bare wafer surface and the depth of the SSD layer that contributes to the formation of in-grown stacking faults (IGSF) during subsequent epitaxial growth. The results show that SiC wafer inspection using the novel LLS method, which introduces this relational equation, enables non-destructive and quantitative evaluation of SSD depth and in-plane distribution.