Papers by Keyword: Epitaxial Layer

Abstract: The quality of the silicon carbide (SiC) epitaxial layer, i.e., layer homogeneities and extended defect densities, is of highest importance for high power 4H-SiC trench metal-oxide-semiconductor field effect transistors (Trench-MOSFET) devices. Especially, yield for devices with a large chip area is severely impacted by extended defects. Previously, devices had to be fully manufactured to effectively gauge the impact of a reduction in extended defect densities in the epitaxial layers on device yield. The production of devices such as Trench-MOSFETs is an extensive procedure. Therefore, a correlation between extended defects in the epitaxial layer and electrical device failure would allow to reliably estimate the impact of process changes during epitaxial layer deposition on electrical device yield.For this reason, n-type epitaxial layers were grown on around 1,000 commercially available 150 mm 4H-SiC Si-face substrates, which received a chemical wet cleaning prior to the epitaxy deposition. Substrates with lowest micro-pipe density from two different suppliers were used. The wafers were characterized with the corresponding device layout for defects utilizing surface microscopy as well as ultraviolet photoluminescence techniques. Subsequently, these wafers were used to produce more than 500,000 Trench-MOSFET devices. All devices have been tested on wafer level for their initial electrical integrity.With these methods a precise correlation between extended defects in the epitaxial layer and electrical failures on wafer level could be found. The influence of different substrates on the defect-based yield prediction regarding the electrical yield on wafer level is discussed. Additionally, a calculated kill-ratio is presented and the severity of defect classes on initial device failure, e.g., stacking faults, and their key failures modes are discussed.

Abstract: We present an epitaxy-based approach for designing a 3C-SiC Capacitive Micromachined Ultrasonic Transducer (CMUT). The design requires to consider a 3C-SiC/Si/3C-SiC heterostructure on a Si substrate. This implies to address different growth steps of SiC on Si and Si on SiC. We present some specific growth related issued, namely the control of selectively grown Si on a masked SiC(100) and the further regrowth of 3C-SiC on a Si (110) layer. The final release of the SiC membrane, to define a CMUT, is also addressed using a simple thermal treatment allowing to suppress several technological steps.

Abstract: The yield of high power 4H-SiC Trench-MOSFET devices, especially for those with large chip area, is largely dependent on the quality of the underlying epitaxial layers and therefore low densities of critical defects are of utmost importance. Different growth conditions for the deposition of epitaxial layers were investigated to reduce the impact of defects on electrical device performance. For this investigation, 12 μm thick n-type epitaxial layers were grown varying growth rates for the buffer and the drift layer in a warm-wall chemical vapor deposition reactor. The defects in the epitaxial layers were characterized utilizing surface microscopy as well as ultraviolet photoluminescence techniques. A quantitative comparison of surface defects and crystallographic defects between the different growth conditions was conducted with these methods. The impact of the growth conditions on the formation of critical defects is discussed in detail. The reduction of critical defects, which resulted in an increase of the predicted die yield, as well as an outlook on future investigations, is discussed.

Abstract: Epitaxial growth of 4H-SiC on 150 mm wafers using 3 x 150 mm multi-wafer CVD has been investigated to realize extremely low defect density on the epitaxial layer in order to achieve stable fabrication of high current devices with large die size. By optimizing the epitaxial growth conditions as well as the improved procedures for the inside the furnace to remain cleaned stably for cumulative growth processes, we have demonstrated an extensive 99% defect free epitaxial inlayer in a 5 mm x 5 mm block evaluation which is having excellent doping and thickness uniformity simultaneously.

Abstract: The resonant frequency and Q factor of the SiC microcantilever were theoretically analyzed and calculated based on the stereotyped basic theories of the cantilever beam, and the relationship between the vibration mode and structure geometries was also simulated. Modal analysis by means of finite element method was performed on millimeter-, micron-and nanoscale microcantilevers, and the results showed that the smaller the microstructure was, the higher the resonant frequency can be obtained. The Q factor can be extracted from hamonic spectra after modal analysis, and the amplitude of Q factor was about 10⁵. This paper shows that SiC epitaxial layers have great potential in microcantilevers.

Abstract: Carrier lifetime in low carrier concentration 4H-SiC epitaxial layers grown on the C-face was enhanced by using carbon implantation and post annealing. The measured carrier lifetime increased with the thickness of the epitaxial layer and was 11.4 µs for the 150 µm thick epitaxial layer. The internal carrier lifetime was estimated as 21 µs from the dependence of the measured carrier lifetime on the epitaxial layer thickness. This value is almost comparable to the reported values of the internal carrier lifetime for the layers grown on the Si-face.

Abstract: Step bunching on a vicinal 4H-SiC (0001) epitaxial layer surface was investigated using low-voltage electron scanning microscopy (LVSEM) and electron channeling contrast (ECC) imaging. LVSEM observations revealed that the step bunching resulted in the formation of atomically flat wide (~250 nm) terraces on the surface, and the terraces tended to form in pairs. The two terraces in paired terraces often showed the same electron channeling contrast as each other, and the contrast of the two terraces, either bright or dark, appeared to be determined by the orthogonal misorientation of substrates. On the basis of these results, the formation mechanism of the step-bunched structure on a vicinal 4H-SiC (0001) surface is discussed.

Abstract: We propose the thermal chemical etching process for Silicon Carbide (SiC) under the Si-vapor ambient using Tantalum Carbide / metal Tantalum composite materials (TaC/Ta). In this process, the high-rate “Si-vapor etching” method is applied to the removal of the surface damage and the formation of epi-ready surface. Over 10μm of “Si-vapor etching” provides smooth surface without latent scratch and low stacking faults density as same as on the CMP after epitaxial growth, which are observed by confocal microscope with differential interference contrast (C-DIC) microscope and Photo-Luminescence (PL) imaging measurement. Furthermore, the low-rate Si-vapor etching method, “Si-vapor ambient annealing” is applied to post-implantation activation annealing process without conventional C-cap. “Si-vapor ambient annealing” provides lower sheet resistance and smoother surface than the C-cap annealing after very high temperature annealing up to 2000 °C.

Abstract: Simple models for Shockley-type stacking-fault formations during 4H-SiC epitaxial growth are proposed. The model consists of the accidentally-faulted mis-stacking and the Shockley single-gliding events. At first, the mis-stacking event caused by imperfect step-flow growth is considered. Then the single-gliding event is followed to make more stable stacking sequences. Simple single-gliding is considered rather than complicated double, triple, or quadruple Shockley gliding. All possible mis-stacking and single-gliding events are considered. All of the reported Shockley-type SFs are derived without excess and deficiency from the proposed models.

Abstract: It is crucial to know the distribution coefficients of chemical elements in melts. This is essential for obtaining a given composition and properties of epitaxial layers grown from the liquid phase, for determining the regimes of high purification of materials obtained by zone melting, for producing the desired gradient of distribution of alloying elements throughout the layers of construction materials treated by chemical-thermal methods, etc. This paper presents the results of computing the distribution coefficient of arsenic during the growth of layers of phosphide-arsenide of gallium from the liquid phase (molten gallium), saturated with phosphorus. We also obtain the dependencies between the distribution coefficient of arsenic, the temperature and the concentration of arsenic inside the gallium melt during the growth of epitaxial layers. As well a practical application of the results with a given gradient of concentration for the gallium arsenide layer is demonstrated.