Papers by Keyword: Epitaxy

Abstract: The detection and classification of SiC Epitaxial extended defects was refined to separate out defective areas that influence device characteristics. Die level defect localization along with defect area calculations were performed on millions of die across product groups. A clear impact of non-killer defects was observed, especially with increasing density and defective area in the die. Specifically, all types of stacking faults caused higher leakage, lower blocking voltage, and increases in ON resistance and threshold leakage. Furthermore, MOSFET devices were affected to a much larger extent than diode devices. Testing die with higher numbers of defects provides insight on device reliability. Analyzing devices with specific counts of BPDs let us quantify the amount of bipolar degradation caused drift by product/voltage classes.

Abstract: A systematic germanium (Ge) and vanadium (V) study on 4H-SiC epitaxial layers is presented. Electrical results of TLM structures which were fabricated on these layers revealed that highly-doped Ge and V-implanted layers showed extremely low specific contact resistivity, down to 2 x 10^-7 Ω.cm². Current flow in the conducting state of Schottky barrier diodes has been successfully suppressed in some implanted layers, with highly V doped samples showing current density values of approximately 1 x 10^-5 Acm^-2 at 10 V. DLTS spectra reveal the presence of germanium and vanadium centers in the respective samples as well as novel peaks which are likely related to the formation of a novel GeN center.

Abstract: In this work, an AlGaN/GaN HEMT structure is grown on a 0.8 μm thick 3C-SiC layer on high resistivity Silicon substrate. The RF propagation losses are investigated and compared with the ones of epi-layers grown directly on Silicon and on 6H-SiC substrates. Short gate length transistors are fabricated using e-beam lithography. In spite of ohmic contact resistance of 0.6 Ω.mm, a saturated current density of 0.7 A/mm at a gate bias of +1V and a transconductance peak higher to 250 mS/mm for 75 nm T-shaped gate transistors are reached on structure with thick 3C-SiC template. Moreover, for the first time, transition frequencies f_T/f_max of 60/98 GHz are reported on such 3C-SiC template.

Abstract: The triangular defect is a common defect in the 4H-SiC epitaxy, which is also one of the killer defects to the 4H-SiC devices. In this paper, the 4H-SiC epitaxial wafer was grown by chemical vapor deposition (CVD). The formation mechanism of triangular defects in silicon carbide epitaxy was analyzed, and the solutions were proposed. Then, the diodes were fabricated on the wafer, and the influence of triangular defects on the forward and reverse I-V characteristics of 4H-SiC diodes was analyzed by tracking the defects map. The results show that the presence of triangular defects can lead to the reduction of the reverse voltage by about 40%, an increase of the leakage current by four orders of magnitude, and an increase of the forward conduction resistance.

Abstract: The studies are devoted to the development of the technology of multilayer incorporation of nanocrystals (NCs) of semiconductor chromium and iron disilicides with a layer density no less than 2x10¹⁰ cm-2, the establishment of the growth mechanism of heterostructures with two types of NCs, the determination of their crystalline quality and optical properties, as well as the creation and study of rectification and photoelectric properties of p-i-n diodes based on them. Morphologically smooth heterostructures with 6 embedded layers of CrSi2 nanocrystals and two types of embedded nanocrystals (with 4 layers of CrSi2 NCs and 2 layers of β-FeSi2 NCs) for optical studies and built-in silicon p-i-n diodes were grown for the first time. The possibility of optical identification of interband transitions in embedded nanocrystals in the photon energy range of 1.2 - 2.5 eV was determined from the reflection spectra and the strongest peaks in reflection from the integrated nanocrystals were determined: 2.0 eV for CrSi2 NCs and 1.75 eV for β-FeSi2 NCs. The created p-i-n diodes have a contact potential difference of 0.95 V, regardless of the type of embedded NCs. At 80 K, an absorption band (0.7 - 1.1 eV) was detected in the diodes, which was associated with carrier photo generation in the embedded CrSi2 and β-FeSi2 NCs. From the spectra of the photoresponse at 80 K, the band gap widths in the NCs were determined: 0.50 eV in CrSi2 and 0.70 eV in the superposition of the CrSi2 and β-FeSi2 NCs.

Abstract: Multi-channel defect detection in epitaxial SiC layers is used to detect and classify various extended defects. The effects of the killer defect category are analyzed on hundreds of production diode and MOSFET wafers. Invariably, the number of these killer defects sets the yield entitlement for each wafer, and electrically, they fall into a few expected failure bins depending on their position on the die. A variety of non-killer defects like Bar Stacking Faults (BSFs), V-type defects, isolated micro-pipe related bumps, stacking faults, scratches and deep pits are identified in over thousand die each, and their effect on fully fabricated diode and MOSFET products are determined at wafer sort. A very high percentage of the die containing these non-killer defects pass all electrical tests including the rigorous Unclamped Inductive Switching (UIS) testing. Specifically, a population of electrically passing die, containing BSFs, are identified and packaged for High Temperature Reverse Bias (HTRB) tests. Every BSF containing die passes both forward and reverse 1000-hour HTRB drift tests.

Abstract: Because the well-known site-competition and step-controlled epitaxy rules cannot reasonably describe all the incorporation processes of the main impurities (Al and N) into 4H-SiC during epitaxy, the concept of replacement incorporation was proposed and applied to explain the experimental results published so far. In this model, the transient formation of C or Si vacancies at the surface or sub-surface of terraces is proposed to play a key role by destabilizing the impurities sitting on them. In addition to the availability of these vacancies at the surface, desorption was proposed to be a very important limiting process for Al incorporation while only occasionally relevant for N incorporation. The main 4H-SiC epitaxial growth parameters are reviewed and discussed according to the proposed replacement model.

Abstract: The future challenges for SiC device technology are cost reduction and increased reliability. A key point to achieve that is the increase of yield during epitaxial layer growth through the reduction of structural defects (such as basal plane dislocations and triangle defects), an increased thickness and doping uniformity, and a high growth rate. Despite significant advancements in SiC epitaxial growth technology, it still constitutes a big challenge to find the optimum working point at which all those requirements are fulfilled. By implementing a new epitaxial layer growth process, we are able to grow basal plane dislocation free epitaxial layers, while the density of other structural defects remains low. Additionally, intra-wafer thickness and doping uniformities of the epitaxial layers are further improved.

Abstract: Inline metrology tools are widely used to detect defects in SiC epitaxial layers. The defect statistics are used in a variety of ways to determine quality, pass/fail and screen affected die. In this work, we document the automated detection and classification of various epitaxial defects based on type and origin. We further classify these categories into killer and non-killer defects and compare them to the electrical yield of Schottky Diodes. The origins of these defects are determined in broad categories, resulting in a clustering and yield-scaling model, which agrees very closely to experimental data. Further, we look at on-wafer screening techniques of potential weak die by both defect tagging and unclamped inductive switching (UIS) stress testing. Successful 1000-hr reliability tests show the robustness of our detection and screening methods.

Abstract: In this work many steps concerning the epitaxial layer growth on 4H-SiC are studied, evaluated and optimized to obtain high quality 4H-SiC epitaxy. The processes evaluated have been studied on a Hot Wall CVD reactor. The first step related to the substrate surface etching has been tuned by choosing the H2 flow, temperature and process time at which most of defects (mainly stacking faults) are not propagated. Then, the buffer layer step has been optimized by increasing the thickness at which an effective reduction of defect density and an improved electrical performance of power devices have been detected. Also, during the buffer layer growth a strong dependence between basal plane dislocations propagation and the growth rate has been observed. A crucial step carefully studied has been the drift layer growth. It was optimized by increasing the growth rate (13<GR<15µm/h) that results in a lower defectiveness, good thickness and doping uniformity. Final stage concerning the cooling of the process has been strongly revisited. A significant decreasing of the morphological defects (carrots, pits) and stacking faults has been observed by slowing the cool down process (~ 25 °C/min).