Papers by Keyword: FPGA

Abstract: Solar panels are a renewable energy source capable of converting sunlight into electricity. The power output from these panels fluctuates with changes in sunlight intensity, affecting the maximum power they can produce. To maintain a stable maximum power output, an automatic controller is essential, and the Maximum Power Point Tracker (MPPT) serves this purpose. The MPPT controller reads voltage, current, and power values from the solar panel to ensure it operates at the Maximum Power Point (MPP). The Perturb and Observe (P&O) algorithm is a reliable MPPT method for stable power tracking, although it has a drawback in terms of speed due to its step-by-step measurement process. In contrast, the Fractional Short Circuit Current (FSCC) algorithm is faster in estimating the MPP value but less accurate in tracking actual power output. Combining the P&O and FSCC algorithms aims to create a method that rapidly determines the MPP value while ensuring stable tracking. The design's implementation uses Verilog Hardware Description Language (HDL) on a Field Programmable Gate Array (FPGA) to create an independent IP-Core MPPT controller, eliminating the need for aprocessor. Implementation results show that the P&O+FSCC algorithm achieves an MPP search speed of about 18 seconds, compared to approximately 55 s for P&O alone, representing a 32.72% improvement.

Abstract: Single-event and multi-bit effects are the result of radiation and ionized particles in extreme settings like space, which can lead to random failures on any electronic component. To keep the functionality of the device unaltered, these must be reduced. FPGA plays a vital role in satellite and aerospace applications in which dynamic reconfiguration essential. Cascaded Integration Comb (CIC) filters are mostly utilized in multidata signal processing and satellite communication systems as low pass filters in rate converter modules. The configuration memory of FPGA used to design CIC filter is affected with soft errors with single and multi-bit due to high radiation in higher altitude and different environment regions. The methods like triple modular redundancy (TMR) is very effective in overcoming single event transients and single-event upsets, but incur area three times of the original module. Scrubbing is a serial process method that goes over each word in memory in search of mistakes that need to be fixed. It entails a non-negligible Time to Detect (TTD) prior to repair, in which time further functionality could happen parallely and jeopardize the system. Thus, effective multi-bit error detection correction of configuration memory in FPGA is essential in maintaining the application to work for an extended time. In this research, built-in multi-bit error correction for FPGA configuration memory is proposed. The proposed work can replace time consuming scrubbing process and high area utilizing TMR for error tolerant design. To safeguard FPGA, a multi-bit error detection and correction system is performed by using multi dimensional parity with minimum area overhead. Furthermore, the suggested method can identify and rectify error when triggered by an interrupt manager reducing time to detect (TTD).

Abstract: Wireless anti-jamming data link was widely applied in modern electronic warfare environment recently. Anti-jamming function of wireless data link was realized by constantly changing the signal carrier frequency according to a specific pseudo-random sequence. Frequency switching time and bandwidth were the main factors of frequency hopping anti-jamming performance. With the development DDS technology, frequency switching time and bandwidth had been improved significantly. The hardware of anti-jamming data link node in this paper was composed of frequency synthesizer module and FPGA control module taking advantage of both DDS technology and FPGA. Frequency synthesizer module was under the control of FPGA to output appropriate frequency carrier signal. FPGA control module is designed in Quartus II software development platform environment. The frequency tuning and control of frequency synthesizer module output signal were operated through serial or parallel I/O ports. Two kinds of configuration mode were designed in FPGA control module: serial configuration mode and parallel configuration mode. Digital signal data process in serial configuration logic and parallel configuration logic of FPGA control module were studied especially. The main function of serial configuration logic and parallel configuration logic were realized to process the digital signal data under appropriate time sequence correctly. By the correct time sequence of reading and writing function, frequency synthesizer module worked well with FPGA control module. Simulation and experiment results showed that anti-jamming data link node outputted stable frequency carrier signals by the excellent processing of digital signal data transferred between FPGA control module and frequency synthesizer module.

Abstract: In this paper, an FPGA-based microwave oven controller design which can be implemented using Altera DE1 development board is presented. The motivation for this work is to explore FPGA for real time applications. First, a microwave oven controller design architecture that could fit into Altera DE1 board, utilizing on-board peripherals is developed. Then, using the proposed architecture, the design is implemented using Verilog HDL. The microwave oven functionalities are demonstrated using Altera DE1 development board by means of Quartus II 13.0 software. The testbenches are created and waveforms are generated using Modelsim 10.1d software. The simulation results for various cases have been presented and the results confirmed that all the basic functionalities of a practical microwave oven can be realized. The proposed FPGA based controller has a high potential for incorporation in microwave ovens.

Abstract: Hybrid simulation, or hybrid testing, is understood here as a numerical technique for investigating dynamic properties of mechanical systems with components that are difficult to model numerically. This technique can be also referred to as hardware-in-the-loop simulation.The idea of hybrid simulation is that the non-linear part of the system that is difficult to model numerically is tested experimentally and the rest of the system is modeled numerically. Therefore two models are created – the experimental model and the analytical model. During the simulation both models are in strict cooperation in order to act like the undivided system.The following paper focuses on utilizing FPGA (field-programmable gate array) in the computations performed in the analytical model. FPGA is an integrated circuit that is configured by the user. Physically FPGA is an array of logic blocks that the user can program and reconfigure interconnects that will allow to connect logic blocks in the desired way in order to perform complex functions. The most important advantages of using FPGA are flexibility, highly parallel data processing (thanks to simultaneous operation of independent circuits), high efficiency and reliability. Therefore complex digital computations that are implemented to FPGA can be executed with great speed.In the presented research the non-experimental part of the mechanical system is modeled using Finite Element Method (FEM). In order to control the experimental model in a closed loop, the FEM computations must be performed in real time. As FEM is computationally demanding method, the computations must be conducted as efficiently as possible in order to enable real-time without losing accuracy. The following paper describes increasing the time performance of the hybrid simulation algorithm by executing it on the microprocessor of a microcontroller equipped with real-time operating system while performing the most computationally demanding operations on the FPGA.

Abstract: This report considers the creation of a controller intended for reconfiguring the artificial intelligence of robotic vehicles. The functional structure of hardware-reconfigurable digital module for intellectual control of robotic vehicles is proposed and further interaction between its functional modules and remote support center in different situations requiring reconfiguration is concerned. The procedures of self-check and self-testing of the hardware-reconfigurable digital module for intellectual control of mobile space-based robots are described, which are necessary to ensure reliability of reconfiguration.

Abstract: A time-to-digital converter (TDC) based on residue number system is presented. This architecture can reduce hardware and chip area as well as power significantly compared to a flash-type TDC while keeping comparable performance. Its proof-of-concept prototype was implemented on FPGA, and the measurement results validate the effectiveness of the proposed architecture

Abstract: This paper presents a system control design on 2 axes “Delta Industrial Robot”. The control system utilizes both the embedded technology and the “Raspberry Pi" which is a low power consumption PC with open source operating system. The user can communicate with the PC and FPGA (Field Programmable Gate Array) via the system GUI interface. The FPGA acts as dedicated hardware to provide both the efficiency and flexibility for the closed-loop servo control system.To calculate all related kinematics equations for the robot, look up table approach has been implemented to reduce the calculation complexity. Python programs are also implemented to create and search the look up tables. The inverse kinematics is the key to find the position of the robot. A test load of 0.2 kg at the velocity of 2.618 m/s, the S.D. of the end effector’s position of the test result is within 0.06 mm.

Abstract: In order to detect weak chemiluminescence signal rapidly and high accurately, a chemiluminescence detection system is designed based on the core chip FPGA. The system uses a static injection mechanism as chemiluminescence reaction conduit. High-performance photodiode converts chemiluminescence signals into electrical signals replacing the traditional photomultiplier tube. It can meet the test requirements while reducing the cost of the detection system. The signal processing and storage system FPGA-based consists of A/D converter module, serial communication module, the keyboard scan control modules and memory modules. Nitrite ions in water samples are detected and the results show that in a certain concentration range the calibration curve of NO_2- concentration and luminescence intensity is linear, the linear regression equation is Y = 0.4148X + 2.6508, and the correlation coefficient is R² = 0.9832. The relative standard deviation values are 2.7%(n=11).

Abstract: In this paper, analysis results of an FPGA (Field-Programmable Gate Array) designed in RTL (Register Transfer Level) shows that does not have a problem in routing. It has many advantages than conventional FPGA developed by the transistor level. However, the crossbar switch of the FPGA designed in RTL has a problem with the direction of the signal. The direction is fixed in one direction unlike the conventional crossbar switch. Routing is analyzed by using the circuit of three input two output.