Papers by Keyword: FPGA

Abstract: This paper introduces auto tuning of proportional-integral-derivative (PID) controllers of DC motor using particle swarm optimization (PSO) method. The DC motor was modeled in Simulink and PSO was implanted on FPGA “cyclone IV E” using the soft processor NIOS II. The results were efficient in reducing the steady state error, settling time, rise time and maximum overshoot in speed control of a DC motor.

Abstract: The FPGA platform is a developing area in the industry applications. With continuous advancement in science and technology, the image quality has entered an era of full-HD. Its resolution reaches 1920x1080 pixels, and its refresh rate comes to 60 fps (Frames Per Second). Taking the 1920x1080 P, 60 fps image sensor as an example, the eye diagram efficacy at both the image input end and the output end were measured. When the input signal was LVDS, the standard value of the eye width and height was 1.092 ns and 100mV respectively. The measured value was 1.297 ns and 149 mV respectively, which are 18% and 49% better than the standard value, respectively. When the output signal was HDMI, the standard [1] of the eye diagram was 424 ps and 400 mV respectively. The measured value was about 540 ps and 600 mV respectively, which are 27% and 50% better than the standard value, respectively. The results of measurement of the electrical characteristics of the system above show that our high-resolution image processing system platform has high reliability.

Abstract: With continuous advancement in science and technology, the image quality has entered an era of full-HD. This study developed a high-reliability image processing system platform, based on the FPGA platform. By using a high-reliability hardware platform development process, and with the aid of the simulation software, this study simulated the transmission integrity of the high-speed digital signals on the PCB. The proposed method was used to build a FPGA-based high-reliability image processing system platform. The implementation in this study, with the length of the Clock and DQS signal line of DDR2 being controlled within 555 mil, was discussed, and the errors were analyzed. The simulated value of the tDQSCK was 195.048 ps, the measured value was 215 ps, and the standard value of the JEDEC was less than 350 ps. Between the simulated value and the measured value, there was only an error of about 9.3%, which meets the reliability requirement. The length tolerance of the signal line laid was 38.5% better than the standard value of the JEDEC.

Abstract: A digital simulation method for the performance degradation signal of rolling bearings is developed based on the analysis of experimental data. A self-organizing map neural network is utilized to build the performance degradation assessment model of the rolling bearings based on characteristic parameter extraction. Wavelet packet decomposition is then implemented to extract the wavelet coefficients in the corresponding performance degradation sensitive band. Different health confidence values are injected into the extracted wavelet packet coefficients, and signals are reconstructed according to the simulation needs to obtain rolling bearing vibration data under different degradation degrees. Understanding the exact mathematical model of the measured object is unnecessary in this method; the method is simple and reliable and helps solve the problem of performance degradation data simulation. Finally, an FPGA-based performance degradation signal simulator is designed by combining the analogy procedure, employed to support the verification process of fault diagnosis and prediction capability.

Abstract: This work presents a hardware implementation of a simple microprocessor; then uses this microprocessor to design a PI controller for PMSM (Permanent Magnet Synchronous Motor) drives. In this paper, firstly, the mathematical model of PMSM drives is illustrated. Secondly, the architecture of a simple microprocessor based on RTL (Register Transfer Level) method is proposed and the VHDL (Very high speed IC Hardware Description Language) is adopted to describe the behavior of the simple microprocessor. Thirdly, a machine code of PI controller based on the proposed simple microprocessor is designed. Finally, a co-simulation by Simulink/ModelSim is applied and verified the performance of the microprocessor-based PI controller.

Abstract: We report on the implementation of a FPGA-based ultra-violet (UV), infra-red (IR) visible (Vis) CCD spectrometer using a linear CCD detector operating at room temperature. The host interface is high-speed USB for data exchange with high-level environments such as Visual Basic, MATLAB and LABVIEW. The high-resolution intensity versus wavelength output is 8-bit digitized for secondary processing using a semi-flash analogue-to-digital converter (ADC) capable of sustained sampling rates of 20Mb/s.

Abstract: A high-performance, low-cost test equipment system for characterization of MEMS switch is to be proposed in this paper, and the purpose is set to master the fundament of the embedded algorithms of the wafer and system production testing. The team has implemented the real-time analysis for MEMS switch, proving the feasibility of the design, based on the original data collected during the dedicated tests, applying the microsystem hardware designed and assembled by the research team, as well as the embedded software. At the end, the framework of the system platform in the future is described.

Abstract: In this work, we are going to search the most thermal and energy efficient technology among 90nm, 65nm, 45nm, 40nm and 38nm technology based FPGA, and also searching the most thermal and energy efficient airflow, and heat sink profile. We are also doing thermal analysis for 273.15K-343.15K temperature. we are getting 31.67%, 75.71%, reduction in leakage power for 250LFM and 58.53%, 75.71% reduction in leakage power for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. There is 84.54%, 85.65%, reduction in junction temperature for 250LFM, 84.90%, 85.65%, reduction in junction temperature for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. In this work, we are using 90nm Spartan-3E FPGA, 65nm Virtex-5 FPGA, 45nm Spartan-6 FPGA, 40nm Virtex-6 FPGA, and 28nm Artix-7 FPGA. We are taking two different airflow of 250LFM and 500LFM. LFM is a unit of airflow. LFM is linear feet per minute. Adder is our target design.

Abstract: In this work, we are we are going to search the most thermal and energy efficient IO Standards among the HSTL family and I2C family on 45 nm technology based FPGA. Here we are also doing thermal analysis for 273.15K-343.15K temperature, while during comparing the different IO Standards, we are taking the improvement level at 283.15K. In leakage power analysis, we are getting 9.09% improvement in HSTL with respect to others and in IO power analysis I2C shows 57.89% improvement with respect to others. In thermal analysis for maximum ambient temperature, we observe 1.79% improvement in HSTL_II as compared to others and in Junction Temperature analysis HSTL_I and I2C are 3.6% efficient than others. HSTL_I has minimum Theta Junction to Ambient Temperature value. In this work, we are using 45nm Spartan-6 FPGA. . We are taking airflow of 250LFM where LFM is a unit of airflow. LFM is linear feet per minute. Adder is our target design.

Abstract: This paper introduces the basic principle of Viterbi code in OFDM system and a new implementation method based on FPGA, on and timing circuit are validated by using of EDA tools Quartus II. The new method is that the Viterbi decoding module is improved,which makes the design of the whole decoding structure can be improved and solves the compatibility problem among the modules. Finally, the simulation results is given and demonstrates that a good Viterbi code can be achieved by using FPGA in OFDM system, which can save the cost, shorten the designing cycle , and is convenient to speed up the listing of products, occupy less hardware resources, and comply with the development trend of modern communication.