Papers by Keyword: FPGA

Abstract: Based on the current international trends in technology of the memory controller, a DDR3 memory controller design plan, the program will be the function of the storage controller further divided into the transport layer and the physical layer, followed by the main module functions and the implementation details are described in detail. The controller can efficiently complete the memory request scheduling, increase the memory bus utilization, thereby improving the memory access bandwidth and reduces memory access latency to provide some reference in the future other support for DDR3 memory digital system design. The final completion of DDR3-based digital test system, the input parallel digital signal judgment, the judgment of data stored in the DDR3 memory and the destination address data read out the analysis.

Abstract: The MIMO technology, namely through many antenna clear signal transmission and the receive, in does not increase the extra band width under the premise, enhanced the channel capacity greatly. Understood the MIMO channel the characteristic, studies the channel modelling method, unified the FPGA parallel characteristic, the design has manufactured one kind based on XILINX FPGA the platform MIMO channel analog meter, through the massive test confirmation, and did with the theoretically simulation performance compares, has confirmed the accuracy.

Abstract: This paper issued a new scheme that passing the configuration information of SRIO to FPGA through EMIF interface, so that two FPGAs can transfer data to each other dynamically for different ways of data interaction. In a word, this paper provides a flexible high-speed transmission scheme for the TD-LTE RF conformance test instrument development.

Abstract: In this article, a design of multi-channel data acquisition system is presented. With FPGA as the core controller, the system can implement logic control over the high-speed ADC and acquire high-speed and high-resolution sample data. Using asynchronous FIFO as a cache, it can transfer data between two different clock domains: ADC data acquisition module and RS485 data module, which helps to improve the work efficiency and data throughput of the system. In the Quartus II development platform, Verilog hardware description language is adopted and finite state machine so that parallel acquisition operation to multi-channel ADC controlled by FPGA can be achieved and the system can become equipped with high-resolution, strong real-timeliness, low noise interference and other advantages. When it comes to the final step, simulation of AD sampling, asynchronous FIFO and RS485 transmission are conducted under the Modelsim environment and on-line testing by Signaltap to the system is synchronously implemented. The validity and reliability of the system are verified.

Abstract: The purpose of this study is to develop the architectural system design of the Six Channels Compact Fuzzy Logic Controller (SCC-FLC) ready to be embedded into the FPGA (Field Programmable Gate Array) for joints of arm robot's manipulator. The FPGA based system design of this study could controlled independently six servo of arm robot manipulators to reduce workload of computer system. The method of this study divided into four steps. The first step, the FLC-P (Fuzzy Logic Controller Processor) block module of single channel C-FLC (Compact Fuzzy Logic Controller) on the previous study is redesigned in architectural system design by adding lots of block modules using multiplexing method. The second step, the module interconnections of system architecture are designed by defining some of inputs and output ports. The third step, the specific function of block modules about working processes is determined based on the definition of input and output ports. The fourth step, sequences of multiplexing processes are determined based on the algorithm of FLC, thus the total processing time of SCC-FLC could be estimated from architectural system design. Architectural system design of SCC-FLC requires external chips are 12bit ADC MAX-186 chip and 12bit DAC MAX-3203 of six chips. The block modules of SCC-FLC are FLC-P, LUT-MBFs (Look Up Table of Membership Function), ADC-I (Analog to Digital Converter Interface), DAC-I (Digital Analog Converter Interface), ECEG (Error and Change Error Generators), SPL (Set Point Latchs) and TAC (Time And Control). The total processing time of SCC-FLC by estimation is 256.2 µS or sampling frequency of 3.907KHz using clock frequency of 100MHz.

Abstract: Speckle pattern interferometry can be used to measure he displacement, strain and vibration, surface deformation and surface roughness. And dynamic laser speckle measurement with high accuracy has been widely used in measurement of surface deformation. Tool breakage is the main bottleneck of high-speed intermittent cutting development, therefore, obtaining stress distribution of milling tools is a base of improving the tool design and tool life. Using a speckle measurement method of double pulsed digital based on FPGA, which involves the laser cutter, tools and CCD, transforms the high-speed dynamic measurement to quasi-static measurement. As a result, we can get two speckle images of front and back milling cutter surface and calculate the deformation ,strain and stress distribution of the tool surface with analysis.

Abstract: The acceleration can be controlled using S-curve acceleration/deceleration algorithm in motion process and the impact of system is decreased in the stage of start or stop. So the S-curve is widely used in CNC or robot system. At present, most acceleration/deceleration algorithms are achieved in PC using strong operation ability of CPU, which increase the delay time of PC. So a simple and efficient S-curve acceleration/deceleration algorithm in FPGA is proposed. This algorithm can share the operation press of PC effectively and achieve flexible control of motion control system.

Abstract: This template explains and demonstrates how to prepare your camera-ready paper for Trans Tech Publications. The best is to read these instructions and follow the outline of this text. Please make the page settings of your word processor to A4 format (21 x 29,7 cm or 8 x 11 inches); with the margins: bottom 1.5 cm (0.59 in) and top 2.5 cm (0.98 in), right/left margins must be 2 cm (0.78 in). This template explains and demonstrates how to prepare your camera-ready paper for Trans Tech Publications. The best is to read these instructions and follow the outline of this text. Please make the page settings of your word processor to A4 format (21 x 29,7 cm or 8 x 11 inches); with the margins: bottom 1.5 cm (0.59 in) and top 2.5 cm (0.98 in), right/left margins must be 2 cm (0.78 in).

Abstract: This paper demonstrates a new strategy for accelerating FPGA realization which is integrated design from model to automated HDL code generation, and it’s applied to a design of Takagi-Sugeno fuzzy logic control (FLC) Systems on vehicle autopilot based on FPGA. The system designed by this strategy accurately guides vehicle to the destination by controlling size and angle of speed.

Abstract: The video capture and preprocessing is the basis of video process system. This paper analyzes the timing of video capture by Camera Link interface based on FPGA, and proposed an automatic error detection approach to avoid error accumulation during the video data capture. Furthermore, by adopting the optimized LUT and pipeline addition, an optimized method for RGB to YCbCr color space conversion (CSC) is presented specifically for the video format preprocessing. Experimental results demonstrate that the strategy we proposed is of high reliability, and it could obtain maximum operation frequency of 334MHz, 3.16 times faster than the direct method.