Papers by Keyword: FPGA

Abstract: Working on low-contrast, extended, time-varying objects such as the solar granulation, solar adaptive optics (AO) system uses correlation algorithms to detect image shift of the Shack-Hartmann (SH) wavefront sensor (WFS) instead of centroid algorithm in night-time adaptive optics system. An real-time image shift detection processor, which consists of a Xilinx FPGA and a TI DSP, has been developed for a low-order solar AO system based on cross correlation coefficient algorithm. Image shift of integer pixels can be calculated in the FPGA and DSP is responsible for parabolic interpolation to obtain subpixel accuracy. The experimental results show that the processor can obtain correct image shift and satisfy the time latency requirement of the AO system.

Abstract: This paper presents a novel closed current control loop of permanent magnet synchronous motor (PMSM). Conventional current control loops need two PI controllers per one PMSM. The paper provides a method for reduction of the resource consumption by using one PI controller for two PMSM. Combining with Black Box Blockset written by Verilog HDL based on Xilinx System Generator, one effective PI controller is designed instead of four PI controllers and simulated using Simulink. The utilization of FPGA resources is verified by Xilinx ISE 14.7 tool. The results show that the proposed method can reduce resource consumption and do not influence system performances observably.

Abstract: The nearest level modulation (NLM) is commonly used in the multi-level multi-module converter (MMC), which need to convert the fractional part of the input sine wave to the digital signal (DPWM). However, the narrow pulse width of digital signal , the frequent change of the digital signal and the frequent instability of output are caused by the sensitive fractional portion of the input, which push Multilevel converter into the position where it has to operate in high frequency and be unstable. In order to solve the problem mentioned above, this paper provides a way called hysteresis comparison to meet the control requirements of precision, adopting the comparison between the fractional part and triangular carrier wave. The approach this study provides is called hysteresis comparison which not only can ensure the stability of the output of the digital signal but also can be able to obtain better digital pulse width by adjusting hysteresis threshold trigger. At the same time, it could ensure the stability and pulse width of the output by means of reducing the frequency of the digital output. The feasibility of this approach has been certified by the simulation of field-programmable gate array (FPGA). Apparently, the actual results show that this method can optimize the control of HVDC Flexible.

Abstract: Aiming at the problem that traditional median filter algorithm cannot process collected images quickly and efficiently, this paper adopts improved median filter and makes use of advantages, such as fast running speed, parallel running of inner program, to design an image preprocessing system with high real time ability and high flexibility. At last, compared with MATLAB median filter simulation figure and multilevel median filter, it has shown that using FPGA to process and improve median filter can not only conduct median filter to images successfully, but also has the ability of fast operation speed and low energy consumption.

Abstract: This system uses the MSP430F6638 and FPGA as the core, includes full bridge rectifier circuit, power factor correction circuit, Boost/Buck circuit and sample circuit. According to the sampling voltage and current value, The FPGA adjusts PWM wave duty ratio of power factor correction chip UC3854, completing single phase AC/DC conversion circuit with a voltage outer closed-loop and current inner closed-loop and active power factor correction (APFC). Test shows that the output voltage can stable in a setting value, with amplitude range ±0.05V, and when load’s impedance changes, this circuit can keep a small voltage adjustment rate and load adjustment rate. We use electronic parameter measurement device to measure the efficiency of AC/DC converter in a specified condition (voltage input Us=24V, current output Io=2A, voltage output Uo=36V), result demonstrates it’s a relatively ideal value. At the same time, under the control of UC3854, the power factor of alternating current input is 0.9734.And when we set the range of power factor between 0.8~1.0, The circuit can automatically adjust the power factor to track the set value.

Abstract: For multi_level multi_module in the flexible HVDC converter (MMC) module capacitor control algorithm is commonly based on nearest voltage level modulation (NLM), this algorithm requires the decimal part of the input sine wave for analog-to-digital conversion by digital signal (digital pulse modulation, referred to as DPWM),in the choice of hysteretic DPWM control signal is better, if the input triangle carrier wave frequency selection is not good, in each digital signal level will cause the output frequency of DPWM is not stable, some DPWM frequency is too high, and some DPWM has no output. In order to solve this problem, to meet the requirements of control precision, the carrier frequency change DPWM triangular wave, the output ideal control signal, the output control signal is analyzed, put forward how to carry out DPWM frequency selection. Through the simulation certified the feasibility of this method, the control method of downloading to the field programmable gate array (FPGA) chip, the results of the actual control operation show that this method can optimize the control of flexible HVDC.

Abstract: In order to improve the development using FPGA solar panels generating speed, through the study on the solar panel maximum power output perturbation method (MPPT) how to develop and how to improve the development efficiency were studied. This algorithm through MATLAB Simulink simulation is confirmed, then use generator to simulate the algorithm, and the algorithm is downloaded into the FPGA, the hardware co_simulation, design of MPPT circuit will be in accordance with the circuit parameters of the modified. Through the hardware circuit operating results, it is proved that the algorithm design of circuit is correct and meet the design requirements, also demonstrate the utility of using generator hardware co_simulation method for the development of FPGA. The development method can improve the design speed, shorten the reliability of control, the development cycle and reduce development costs, achieve a fully compatible and replace physical circuit.

Abstract: Space target detection under the background of stars is one of the key techniques in space based optical measurement. In this paper, we proposed a space target detection algorithm based on star identification. First, the centroid of stars and space target is extracted by FPGA. Then, DSP accomplish space target detection based on the centroid data. Result shows that this method have a good effect on the space target detection.

Abstract: In this paper, we put forward an innovation method of high-speed and real-time error diffusion, which is based on Floyd-Steinberg algorithm. The design introduces LUT(look up table) and pipeline technology instead of complex multiplication operations, which accesses to the memory frequently. The whole design uses Verilog HDL language to program and Quartus ii 8.0 to synthesize and layout. At the end of the paper, we use a 48 pixel as an example, then simulate and verify it on the Modesim, which can prove the correctness of the design. Compared with the standard Floyed-Steinberg algorithm, this design can reduce the computation complexity, use a smaller memory space to exchange lots of logic units and increase the throughput of the algorithm. Besides, it has the advantages of good reconfigurability, simple hardware structure and high real-time.

Abstract: The digital clock is a clock designed by digital circuit. Now, there are some limitations in the use and regulation of the digital clock in the large square. In this paper, the infrared remote-controlled digital clock based on FPGA can solve this problem well. This digital clock is composed of three parts: infrared remote control module, main circuit of the digital clock and function modules. And it is designed by the VHDL hardware description language, in the Quartus II software development environment.In addition, the digital clock has many extended functions, such as the hour timekeeping, alarm clock and temperature measuring. Besides, it has many advantages, including stable system , simple structure, short development cycle, fast speed and the strong usability.