Papers by Keyword: Field-Effect Transistor

Abstract: In this study, ZnO nanowire field-effect transistor (FET) with an aluminium-doped ZnO (AZO) and an aluminium (Al) dual layer source and drain contact are fabricated and temperature dependent characteristics in the range of 200 – 300 K are analyzed through experimental measurements. The effect of temperature on threshold voltage, subthreshold slope, transconductance, and field effect mobility are analysed. The transfer curve exhibits a parallel shift toward a negative gate voltage direction with a negative shift of the threshold voltage, an increase in the subthreshold slope, and a field-effect mobility as the temperature rises. The electrical properties of the transistors demonstrate typical behaviour at various temperatures.

Abstract: Core–shell Si/SiC nanostructures appear as promising building blocks for sensing applications, thanks to the high chemical stability of SiC coupled with the semiconducting properties of Si. In order to optimize the fabrication process of such structures, Si nanowires were coated with a thin SiC layer, and integrated as back-gated field-effet transistors. Two approaches for the fabrication of the SiC shell were then investigated. The first approach involves chemical vapor deposition of amorphous SiC on Si nanowires, without the need for masking; the second approach involves carbonization of Si surfaces to produce a thin crystalline SiC layer, but requires a larger thermal budget. The resulting structures were analyzed using high-resolution transmission electron microscopy (HR-TEM), and the devices were characterized electrically. Electrical characterization shows that the carbonization approach induces a dramatic decrease in drain-to-source current associated with gate leakage, whereas the electrical performances were preserved in the case of chemical deposition.

Abstract:

Dip-coating is a conventional solution processing technology to prepare large-area films at a low cost and with cheap facilities. For semiconductor film processing, crystal orientation and thickness uniformity are the primary factors that determine the film quality and its electrical performance. These requirements are readily satisfied with the dip-coating method because the film morphology can be effectively optimized by tuning the withdrawal speed. This work optimizes the withdrawal speed for the dip-coating of patterned semiconductor films of 400×500 mm² as well as that for film dip-coating on the whole surfaces of the substrate. For both experiment, optimized electrical mobility is achieved at the same withdrawal speed, however, the random crystal orientation of the patterned films causes a remarkable decrease in device performance.

Abstract: The potential impact of high permittivity gate dielectrics on the performance of a ballistic nanoscale CNTFET is studied over a wide range of dielectric permittivities with low temperatures ranging from room temperature down to 100 K. Using the non-equilibrium Greens function (NEGF) formalism. Device characteristics such as I_ON/I_OFF current ratio, threshold voltage, the drain induced barrier lowering (DIBL). The effects of temperature varying are also examined.

Abstract: The electrical transport properties of C70 and C60 fullerene peapods are investigated. We report the fabrications and performances of field-effect transistors (FETs) based on C70 and C60 fullerene peapods. A large percentage of the fullerene peapod-FETs we fabricated exhibit ambipolar characteristics with high Ion/Ioff ratio at room temperature in air. The origin of ambipolar behavior is qualitatively discussed.

Abstract: Fabrication of flexible device structures and nanoscale size definition are presently among the most important and ambitious development goals in the IT field. We have recently prepared the vertical nanowire field effect transistor in the flexible polymer foils based on ion tracks. The high-energetic fast heavy ions were used to irradiate the 8μm PET foils and then the chemical etching method were employed to prepare cylindrical channels in these PET foils. These channels were subsequently filled with insulator material and semiconductor, and then provided with suitable metallic contacts, to obtain a vertical field-effect transistor device. Preparation and first electronic results on this new device are reported. Typically over 107 transistors per cm2 with the devices’ diameter of ~100 nm can be obtained in this technique. The fabrication does not require lithography on the scale of a single transistor, and is suitable for large-area and flexible applications.

Abstract: We demonstrate the fabrication and the electrical transport properties of single crystalline 3C silicon carbide nanowires (SiC NWs). The growth of SiC NWs was carried out in a chemical vapor deposition (CVD) furnace. Methyltrichlorosilane (MTS, CH3SiCl3) was chosen as a source precursor. SiC NWs had diameters of less than 100 nm and lengths of several μm. For electrical transport measurements, as-gown SiC NWs were prepared on a highly doped silicon wafer, pre-patterned by a photo-lithography process, with a 400 nm thick SiO2 layer. Source and drain electrodes were defined by e-beam lithography (EBL). Prior to the metal deposition (Ti/Au : 40 nm/70 nm) by thermal evaporation, the native oxide on SiC NWs was removed by buffered HF. The estimated mobility of carriers is 15 cm2/(Vs) for a source-drain voltage (VSD) of 0.02 V. It is very low compared to that expected in bulk and/or thin film 3C-SiC. The electrical measurements from nanowire-based field effect transistor (FET) structures illustrate that SiC NWs are weak n-type semiconductor. We have also demonstrated a powerful technique, a standard UV photo-lithography process, for fabrication of SiC nanowires instead of using EBL process.

Abstract: We report on simple techniques for extracting the electrical properties of 1-dimensional semiconductor nanowires using standard ultraviolet (UV) photo-lithography instead of e-beam lithography (EBL), which is a commonly used technique for the fabrication of nanoscale electrical devices. For electrical transport measurement the gallium nitride nanowires (GaN NWs) were prepared by a horizontal hot-wall chemical vapor deposition (CVD) with metallic Ga and NH3 gas for Ga and N sources, and GaN nanowire field effect transistor (FET) structures on a 8×8 mm2 silicon wafer were fabricated by ordinary 2-mask photo-lithography processes. The estimated carrier mobility from the gate-modulation characteristics is on the order of 60 ∼ 70 cm2/V⋅s. We found that our approach is a powerful and simple technique to extract the electrical properties of semiconductor nanowires. The material characteristics of GaN nanowires are also discussed.

Abstract: Due to a number of advances in molecular biology, cell and tissue culture in combination with more sensitive methods to transduce biological signals, it has become increasingly feasible to detect unknown toxicity or pharmacological effects by using biological systems which are electrically coupled to micro- or nanoelectrodes or field-effect transistors (FETs). The coupling of biomolecules with electronic devices is demonstrated. In order to identify the contributions of the various cell signals we have investigated the coupling of cardiac myocytes with FETs. On the other side such systems can also be used to study the very basics of distributed information processing by interfacing cultured neuronal networks with microelectronic devices.

Abstract: Utilizing an very sensitive electron spin resonance (ESR) technique, spin dependent recombination (SDR) we have identified interface and near interface trapping centers in 4H and 6H SiC/SiO2 metal oxide semiconductor field effect transistors (MOSFETs). We extend our group’s earlier observations on 6H devices to the more technologically important 4H system and find that several centers can play important roles in limiting the performance of SiC based MOSFETs.