Papers by Keyword: Field Effect Mobility

Abstract: This study evaluates the performance and reliability of SiC n-and p-MOSFETs across a temperature range from room temperature up to 400°C, focusing on field effect (FE) mobility and threshold voltage variations under high thermal and bias stress conditions. By analyzing the variations in field effect mobility and threshold voltage under different stress conditions, our study illustrates distinct behaviors between devices with thermally grown oxides and those with chemical vapor deposited (CVD) oxide layers, underscoring significant differences in long term performance. Results indicate that while n-MOSFETs maintain threshold voltage shifts below 3% and exhibit robust characteristics up to 400°C, p-MOSFETs exhibit permanent threshold voltage shifts of up to 10% and mobility reductions of 15% particularly above 300°C DC stress. The 2 nm ultrathin thermal (UT) followed by 40nm CVD SiO₂, outperform thermal oxides, sustaining less degradation in mobility and less shift in threshold voltage under bias temperature instability (BTI) conditions at voltages up to ±25V and temperatures as high as 400°C. This research advances SiC CMOS technology by confirming that SiC n-MOSFETs are ready for high-temperature circuit applications, while highlighting the need for further improvement in p-MOSFETs to enhance their reliability under extreme conditions.

Abstract: This article presents an innovative approach to achieve a high channel mobility for 4H-SiCp-MOSFET via dielectric-semiconductor interface engineering involving atomic layer deposition(ALD) of ultrathin B₂O₃ and SiO₂ stacks. The application of ultrathin boron oxide via ALD introducesa highly manufacturable solution for the passivation of SiC interface. The interface states near valenceband reduces the channel mobility for SiC p-MOSFETs and increases the threshold voltage. Theintroduction of ultrathin B₂O₃ interlayer reduces the threshold voltage and improves the field effectmobility to 12.60 cm²/Vs while the p-MOSFET without the interlayer provides the mobility of 8.91cm²/Vs. This work also includes the optimization of the post-deposition annealing (PDA) conditionsspecific to ultrathin B₂O₃ and bulk SiO₂ dielectric stack to obtain high field effect channel mobilityfor SiO₂/SiC p-MOSFETs.

Abstract: In this paper, the effect of different post oxide deposition nitridation processes in NO on n-channel lateral MOSFETs fabricated on implanted 4H-SiC were investigated. In particular, the electrical behavior of the MOSFETs was deeply investigated not only in terms of SiO₂/SiC interface state density and field effect mobility, but also considering the threshold voltage stability effect. The aim of this work was to explore to which extent post oxide deposition annealing in NO is beneficial for the MOS interface behavior and when their detrimental effects start to become predominant on the device performances. Here, the separation of the trapping states at the interface – either close to the conduction and valence band edges – and the near interface oxide traps are reported for the different duration of the post oxide deposition annealing. In fact, cyclic gate bias stress was employed in order to analyze the behavior of the trapping states and to correlate them with the variation of the benefits in terms of the channel mobility (that saturates at about 80 cm²V^-1s^-1), and on the threshold voltage instability effect. In particular, prolonged PDAs may induce an increase of the amount of trapping states close to the valence band edge and inside the insulator of about 20% and 50 %, respectively.

Abstract: The SiO₂/SiC interface quality has a significant effect on the performance of 4H-SiC MOS devices. The introduction of nitrogen to the SiO₂/SiC interface is a well-known method for reducing the interface state density (D_it). In this study, we introduced nitrogen to the SiO₂/SiC interface by forming SiN_x films using atomic layer deposition (ALD) and thus improved the interface quality. O₂ annealing with a SiN_x interface layer of optimal thickness enhanced the field effect mobility.

Abstract: This paper presents and analyse the experimental results of 4H-SiC(0001) lateral MOSFETs and MOS capacitors with gate oxides grown directly in N₂O environment or in O₂ ambient followed by a N₂O post oxidation annealing process. Different nitridation temperatures of 1200°C, 1300°C, 1400°C and 1500°C have been investigated. Results have demonstrated that at high temperature (>1200°C) there is a significant improvement in the interface trap density (~1.5×10¹¹ cm^-2eV^-1 at 0.2 eV) and field effect channel mobility (19 cm²/V.s) of 4H-SiC MOSFET compare with those at lower temperature (1×10¹² cm^-2eV^-1 at 0.2 eV and 4 cm²/V.s). Among those nitridation temperatures, 1300°C has found to be the most effective in increasing the field effect channel mobility and reducing threshold voltage.

Abstract: The influence of contact thickness on electrical performance of bottom gate Organic Field Effect Transistor (BG-OFET) with staggered and planer structures is studied in this paper. Two dimensional device simulation is performed with identical dimensions for both devices which show a good agreement between simulated and measured results. Contact thickness is varied from 0nm to 20nm for planer and staggered structures. The electrical characteristics are strongly affected by the contact thickness variation. With increasing contact thickness, the threshold voltage shifts from negative to positive. The simulation results indicate that saturation current value of staggered structure is higher than that of planer. Although the current does not increase in staggered structure due to its increasing contact thickness, while the current in planer structure increases up to three times. However, current in planer is still below the current in staggered structure. The extracted field effect mobility and current on-off ratio at 20nm electrode thickness for staggered structure is 0.67 cm²/V.s and 10⁸, respectively. It has been observed that the field effect mobility, threshold voltage, sub-threshold slope, transconductance and current on-off ratio can be modified by varying contact thickness. Analysis of the results clearly demonstrates the significance of controlling the contact thickness in planer and staggered OFETs. It even offers a way to control OFETs parameters.

Abstract: In this paper the electrical and structural characteristics of n-MOSFETs fabricated on 4H SiC with a process based on nitrogen (N) implantation in the channel region before the growth of the gate oxide are reported for low (5x1018 cm-3) and high (6x1019 cm-3) N concentration at the SiO2/SiC interface. The electron mobility and the free carrier concentration in the MOSFET channel were evaluated by Hall effect measurement. The MOSFETs with the higher N concentration had the best electrical characteristics in terms of threshold voltage and field effect mobility, in spite of a lowering of the electron mobility in the channel. The latter is a negative drawback of the fabrication process that probably can be ascribed to an incomplete recovery of the implantation damage or to a high density of interstitial N atoms present in the channel region. In fact, the MOSFETs with the superior electrical performances were fabricated with the higher N+ dose and the shorter thermal oxidation time. However, no evidence of extended defects, clusters or nano-particles in SiC at the interface with the gate oxide was found in every SiC MOSFETs devices observed by electron transmission microscopy

Abstract: We have comparatively characterized the electrical characteristics of 4H-SiC and 2H-GaN MOS capacitors and FETs. While progressive refinement of gate oxide processes, notably with NO anneal, has resulted in better threshold voltage control, reduced subthreshold slope and higher field-effect mobility for 4H-SiC MOSFETs, we have recently reported more superior MOS parameters for 2H-GaN MOSFETs. In addition, we have performed MOS-gated Hall measurements to extract the intrinsic carrier concentration and MOS mobility, indicating that both less channel electron trapping and scattering take place in 2H-GaN MOSFETs.

Abstract: In this paper, we present the effects of MOS channel processing on the threshold voltage and the MOS field effect mobility of 4H-SiC MOSFETs. By increasing the p-well doping concentration by two orders of magnitude, the threshold voltage could be shifted positive from 0V to 5 V when a thermal oxide layer with NO post oxidation anneal was used as the gate dielectric layer. However, a severe degradation of MOS field effect mobility, decreasing from 37 cm2/Vs to 5 cm2/Vs, was also observed. Using a different processing technique, which uses a deposited oxide layer with an NO anneal, a threshold voltage of 7.5 V and a MOS field effect mobility of 15 cm2/Vs could be achieved. A 10 kV, 1 A power DMOSFET was demonstrated with this technique. A DMOSFET turn-off voltage of 5.25 V was measured at room temperature, which shifted to 3.0 V at 250oC, providing acceptable noise margins throughout the operating temperature range.

Abstract: Post-oxidation anneals that introduce nitrogen at the SiO2/4H-SiC interface have been most effective in reducing the large interface trap density near the 4H-SiC conduction band-edge for (0001) Si face 4H-SiC. Herein, we report the effect of nitridation on interfaces created on the (11 20) a-face and the (0001) C-face of 4H-SiC. Significant reductions in trap density (from >1013 cm-2 eV-1 to ~ 1012 cm-2 eV-1 at EC-E ~0.1 eV) were observed for these different interfaces, indicating the presence of substantial nitrogen susceptible defects for all crystal faces. Annealing nitridated interfaces in hydrogen results in a further reduction of trap density (from ~1012 cm-2 eV-1 to ~5 x 1011 cm-2 eV-1 at EC-E ~0.1 eV). Using sequential anneals in NO and H2, maximum field effect mobilities of ~55 cm-2 V-1s-1 and ~100 cm-2 V-1s-1 have been obtained for lateral MOSFETs fabricated on the (0001) and (11 20) faces, respectively. These electronic measurements have been correlated to the interface chemical composition.