Papers by Keyword: Field Programmable Gate Array (FPGA)

Abstract: This paper presents an FPGA architecture for the 1-D integer transform of the latest video coding standard, the High Efficiency Video Coding (HEVC). The design employs hard multipliers in dedicated DSP slices, which are already embedded into an FPGA die, to gain high throughput and save general purpose LUTs. The proposed architecture can support 4x4, 8x8, 16x16, and 32x32 transform. A multiplier sharing scheme is introduced to reduce the total number of required DSP slices in order to be able to fit the design onto a Spartan-3A FPGA. The design can reach a maximum throughput of 1,692 Msamples/s irrespective of the transform size, which is enough to encode 8K (7680x4320) videos at 30 fps. This work is a pioneer research that utilizes the dedicated multipliers on FPGAs in the design of the HEVC transform.

Abstract: A new transceiving protocol is designed for an FSO communication system, and it’s discussed from the transmitting protocol and the receiving protocol. Different from wired communication, a FSO system modulates the data on a narrow beam of laser transmitting through the free space or the atmosphere, and the protocol is optimized for terrestrial FSO links. Due to the complex composition and activity of the atmosphere, this signal channel brings in great influence on the transmitting laser in it. The function of the receiving protocol includes filtering and synchronizing the input serial data stream, paralleling the serial data stream, decoding the input data, error checking, and exception handling and interfacing the outer receiver with a parallel port. The transceiving protocol could be programmed into a single FPGA chip to improve system integrity and reduce the system cost. We also test the hardware platform and communication protocol and give the waveform. The experiment and Simulation prove that the protocol presented can work well at a certain bit rate scale.

Abstract: This paper presents an improved approach to Triple Modular Redundancy (TMR) which concerns don’ t care bits of LUT configuration bits and hence classifies the set of LUTs into SEU-sensitive and SEU-insensitive. Unlike the full TMR approach, the improved approach only triplicates SEU-sensitive LUTs and can greatly reduces the area overhead while maintaining the circuit reliability. The proposed approach is thoroughly tested on the MCNC’91 benchmarks. Compare with the full TMR method the proposed scheme can reduce the area overhead by 26.6% on average, at the same time the circuit reliability only reduced by 9.1 %. The improved approach can also increase mean time between failures (MTBF) by an average of six times more than the original circuit.

Abstract: This paper introduces the field programmable gate array (fpga) application in high-speed visual inspection system.ALTERA EP1K30QC208-2 are used in the system for system calculation and control of the core, to perform high-speed real-time visual detection algorithm, this paper adopts a yawning based on eye closure and to detect driver fatigue, the method of in YCr, Cb in the color space using gaussian model skin detection of human face area, in the face of a gray binarization figure using a priori knowledge of facial features geometry in rough positioning the human eye, eye contour are obtained by region growing and morphological operation and calculation of the closure of the eye;Best threshold detection lips when using lip color roughly locate the lips, on the basis of accurate positioning lips by face grey value characteristics, and then through the mouth level to determine whether a driver yawn;Based on the two characteristics of driving fatigue, experiments show that this system detection speed, excellent versatility, and can improve the detection accuracy.

Abstract: The paper proposes a novel of fully integrated microprocessor (μP), microcontroller (μC) and field programmable gate array (FPGA) robot controller that combines their processing power to fully control all functions of a linear Delta robot. The μP computes the heavy floating point Mathematics including the control law and all robot kinematics at 1 kHz rate while FPGA processes all digital signals from/to the digital sensors and actuators in parallel. At the same time, the μC interfaces with analog I/O and personal computer and passes the signals to the μP via FPGA. The proposed controller is effectively used to control a robot. The experimental results demonstrate the performance of the proposed controller.