Papers by Keyword: Floating Gate

Abstract: In this paper a low voltage FGMOS analog multiplier is proposed that uses a follower voltage flipped (FVF), which dominates its operation. In order to reduce the power supply of the multiplier, floating gate CMOS transistors (FGMOS) are used. Theoretical steps of the FVF design are presented together with its simulation. The output of the FVF is insensitive to the device parameters and is loaded with a resistive load. The multiplier design consists of two FVF cells, two current sensors FVF and one Gilbert cell multiplier. The results show that the proposed multiplied in a 0.13μm CMOS process exhibits significant benefits in terms of linearity, insensibility to device parameters, bandwidth and output impedance. The power supply is 0.8V and a power consumption of 181μW.

Abstract: Thin film transistors with nanoparticles silicon floating-gate are fabricated by plasma enhanced chemical vapor deposition. It should be noted that SiO₂ acts as both a tunneling and a blocking layer. Meanwhile, some np-Si dots are embedded within SiO₂ layers. The electrical characteristic of the devices are measured by semiconductor parameter analyzer at room temperature. These Thin film transistors show a good device performance with a high charge-carrier mobility of 33 cm²/vs and a large on/off ratio of 1.2×10⁶. Moreover, the capability of written and erasing was demonstrated. This indicates that thin film transistors can be operated as rewritable nonvolatile floating gate memory devices.