Papers by Keyword: Forward Voltage Drop

Abstract: This work explores the role of implantation depth in suppressing bipolar degradation of 4H-SiC PiN diodes through proton implantation. Targeting depths aligned with active basal plane dislocations (BPDs) effectively reduces stacking-fault expansion, as confirmed by electroluminescence imaging [1,2]. From these observations, we quantified the effective range of suppression in both depth and safe operating current density. Room-temperature proton implantation (170keV, 1×10¹⁶ cm^-2) into the buffer reduced forward-voltage drift ΔV_F by 97% at 600A/cm². The implanted diode extended the safe operating current range to 1300A/cm², ~200A/cm² higher than the reference, confirming effective suppression of bipolar degradation. Once the suppression barrier, defined as a critical excess hole density threshold, was exceeded, the proton-implanted diode exhibited explosive basal plane dislocation activity, leading to the formation of multiple bar-shaped stacking faults. These active BPDs are located deeper than the proton-implant tail, at a depth of around 11.4µm; however, the threshold hole density required for their activation remains approximately the same (~ 4×10¹⁶ cm^-3) [3].

Abstract: In this paper, a method for suppressing bipolar degradation through proton implantation was investigated. Previous work suggests implantation applied to the full thickness of the epi layer, which results in unwanted defects leading to a deterioration in performance. In this work, proton implantation to the buffer layer was successful in reducing the forward-voltage drift ΔV_F of the fabricated SiC PiN diode by 85% at a current density of 800A/cm², when applying room temperature (RT) proton irradiation at a dose of 1×10¹⁶ cm^-2. Irradiation solely to the buffer layer keeps the deterioration of forward current performance to a minimum, while the fabricated SiC PiN diodes are more robust against bipolar degradation at higher current density. In addition, RT proton irradiated PiN diodes show full recovery from their bipolar degraded characteristics within 2.5 h of annealing at 350 °C under vacuum. This indicates proton irradiation alters the crystal structure for the stacking fault (SF) to “shrink” back with ease to their initial basal plane dislocations (BPD) state.

Abstract: Novel diode structure which looks like DMOSFETs with the gate-shorted to n⁺ source has been developed for the first time. The lateral JFET channel as a built-in channel instead of gate oxide is integrated and it is pinched-off under the zero bias condition. As JFET diode decreases the forward voltage drop using JFET channel efficiency rather than the cell pitch reduction or the increase of doping concentration in n-SiC drift region, V_F and capacitive charges which have a trade-off relationship typically could be decreased simultaneously and a better switching performance is also expected accordingly. Figure-of-Merit (=V_F×Q_C) of the proposed JFET diode has been improved by 20.2% in average compared to that of JBS diode and this FOM would be the best in class among 1200V SiC diode products.

Abstract: The 10 kV silicon carbide p-channel insulated gate bipolar transistors (IGBTs) with low forward voltage drop (V_F) have been fabricated and characterized successfully. The novel edge termination structure of Four-Region Multistep Field Limiting Rings (FRM-FLRs) and the optimum JFET region design proposed in our previous work is adopted to improve the blocking performance and the on-state characteristics. The fabricated device with a chip size of 6 mm × 6 mm and an active area of 0.16 cm² exhibits a high blocking voltage of -10 kV with a small leakage current below -200 nA. Meanwhile, a low forward voltage drop of -8 V at the collector current of -10 A with a gate bias of -20 V is obtained at room temperature, corresponding to a current density of 62.5 A/cm². Besides, a lower gate leakage current is measured less than 2 nA at the gate voltage of -30 V. Experimental results demonstrate that a better trade-off between the blocking voltage and the on-state characteristics is achieved for the fabricated device, which is desirable for the high power applications.

Abstract: This paper presents the design and fabrication of 1200V-rated SiC JBS diodes in a manufacturing environment. Various designs of p⁺-grids and edge termination structures were proposed and fabricated on 6-inch SiC substrates. Experimental results show that deeper p⁺ n junctions are necessary to reduce the leakage current in blocking mode of operation. It was also demonstrated that the hybrid-JTE edge termination structure is very efficient to provide a near-ideal breakdown voltage. Ti and Ni Schottky metals were compared with respect to forward voltage drops and reverse blocking behaviors at high temperatures up to 200 °C.

Abstract: Implantation-free mesa etched ultra-high-voltage 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. The diode’s design allows a high breakdown voltage of about 19.3 kV according to simulations. No reverse breakdown is observed up to 13 kV with a very low leakage current of 0.1 μA. A forward voltage drop (V_F) and differential on-resistance (Diff. R_on) of 9.1 V and 41.4 mΩ cm² are measured at 100 A/cm², respectively, indicating the effect of conductivity modulation.

Abstract: Implantation-free mesa etched 10+ kV 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. An area-optimized junction termination extension (O-JTE) is implemented in order to achieve a high breakdown voltage. The diodes design allows a high breakdown voltage of about 19.3 kV according to simulations by Sentaurus TCAD. No breakdown voltage is recorded up to 10 kV with a very low leakage current of 0.1 μA. The current spreading within the thick drift layer is considered and a voltage drop (V_F) of 8.3 V and 11.4 V are measured at 50 A/cm² and 100 A/cm², respectively. The differential on-resistance (Diff. R_on) of 67.7 mΩ.cm² and 55.7 mΩ.cm² are measured at 50 A/cm² and 100 A/cm², respectively.

Abstract: We successfully fabricated 13-kV, 20-A, 8 mm × 8 mm, drift-free 4H-SiC PiN diodes. The fabricated diodes exhibited breakdown voltages that exceeded 13 kV, a forward voltage drop of 4.9–5.3 V, and an on-resistance (R_onA_active) of 12 mW·cm². The blocking yield at 10 kV on a 3-in wafer exceeded 90%. We investigated failed devices using Candela defect maps and light-emission images and found that a few devices failed because of large defects on the chip. We also demonstrated that the fabricated diodes can be used in conducting high-voltage and high-current switching tests.

Abstract: 13-kV 4H-SiC PiN diodes were fabricated on 4° and 8° off-axis substrates and their electrical properties were examined. Small test PiN diodes with various JTE concentrations were fabricated and the dependence of JTE concentration was examined. The highest breakdown voltages were 14.6 and 14.1 kV at a JTE1 concentration of 1.9 × 10¹⁷ cm⁻³ for both the 4° and 8° off-axis substrates. Based on the results, 4 mm × 4 mm SiC PiN diodes were successfully fabricated and exhibited avalanche breakdown voltages of 14.0 and 13.5 kV for the 4° and 8° off-axis substrates, respectively. Forward voltage degradation was larger for the 8° off-axis substrates.

Abstract: This paper presents a study of performance and scalability of 8kV SiC PIN diodes focusing on area-dependent yield and sensitivity to material properties variation. Successfully fabricated 18 and 36 mm2 SiC-PiN diodes exhibited avalanche breakdown above 8 kV and < 5V forward voltage drop at 100 A/cm2 current density. The fast switching operation of these diodes up to ~5 kHz frequency is evidenced by reverse recovery measurements with by double-pulse inductive switching tests. The devices exhibit 0.142 and 0.169 uC/cm2 stored charge at room temperature and 125oC, respectively, when turned-off from Jf = 100A/cm2 to Vr = 2.1 kV. The measured diode breakdown voltage exhibited location and size dependent yield, indicating the necessity of material quality improvements for production.