Papers by Keyword: Gate Oxide

Abstract: This work investigates the impact of different gate oxide fabrication schemes on the electrical characteristics of 4H-SiC planar MOSFETs. Three processes were implemented: (1) 50 nm thermal oxidation with NO annealing at 1350°C, (2) 50 nm ALD-grown oxide with NO annealing at 1250°C, and (3) a stacked 20 nm thermal/30 nm ALD oxide structure with NO annealing at 1250°C. Electrical characterization included I_dV_g, CV, and I_gE_ox measurements. Results show that Condition 1 exhibits the lowest leakage and best uniformity, and demonstrates strong oxide integrity without soft breakdown events. In contrast, Condition 2 and 3 show increased leakage, higher variability, and evidence of soft breakdown, suggesting greater interfacial weakness. However, a surprising trend was observed in the CV analysis: Condition 2’s flat band voltage (VFB​) is closest to the ideal 0V, indicating a lower fixed charge density than Condition 1 [1], which has the most negative VFB​ (≈ -2V). The hysteresis results further highlight differences, with Condition 3 showing the largest hysteresis window (ΔVth​=0.13V). These findings suggest that while the ALD process coupled with a lower-temperature NO anneal (Condition 2) can effectively reduce fixed charges, it does not fully eliminate interfacial defects responsible for increased leakage and soft breakdown. Our results underscore the complex trade-offs in different fabrication schemes, emphasizing that careful interface engineering beyond conventional NO annealing is required to ensure reliable performance in SiC MOSFETs.

Abstract: The aim of this study is to investigate the overcurrent turn-off robustness limit of SiC MOSFETs from three different manufacturers with three different cell technologies up to very high turn-off currents to determine a possible destruction limit and failure type. The influence of the negative gate-source voltage (V_GS,off) was studied because of the high drain-source overvoltage in connection with the decreased V_GS,off, which is the most critical point for the gate oxide field stress for the different cell technologies. All measurements were performed at a positive gate-source voltage (V_GS,on) above the specified datasheet values to reach high currents without channel pinch-off. In addition, the influence of temperature on the overcurrent robustness was studied. Finally, TCAD simulations were performed to determine the reason for the failure mechanism under the overcurrent turn-off conditions. All the manufacturer devices can withstand several times higher gate-source voltages under overcurrent conditions than the values recommended in the datasheet.

Abstract: In this work, a comparison of standard bulk 4H-SiC epi wafers and Soitec's SmartSiC™ wafers as well as the influence of RTA processing was conducted. For this, MOS capacitors were processed using thermal gate oxide paired with a polycrystalline gate electrode. Subsequent High temperature steps were avoided until an RTA process was performed on some of these wafers. To investigate the oxide quality on all wafer and process splits, CV-, time-zero dielectric breakdown and constant-current stress time-dependent dielectric breakdown measurements were carried out. For the examination of bulk wafers and SmartSiC™, no relevant differences in terms of yield, oxide quality, interface state density and reliability were found. In contrast, RTA processes seem to create a shift in flat band voltage and also lead to a reduction in oxide lifetime. The V_FB shift could partially, but not completely, be explained by addition activation of dopants in the polysilicon electrode. The influence on the oxide reliability, however, is still unclear.

Abstract: In this study we analyzed the physical mechanisms governing time-dependent dielectric breakdown (TDDB) and we used TDDB physical model of dielectric breakdown, implemented in the defect-centric Ginestra® modeling platform, to deconvolute the intrinsic material properties effects and geometry feature impact on the gate oxide (GOx) and SiC-device breakdown.

Abstract: Etching active area by dry etching method can precisely control the length and width of the devices, but it may damage the SiC surface. In this paper, we fabricated metal-oxide-semiconductor capacitors (MOSC) using different etching methods to compare the effect of etching methods on the SiO₂/SiC interface and dielectric breakdown. It is observed that dry etching will degrade the surface roughness of SiC and the interface state density at the SiO₂/SiC interface. Post-oxidation NO annealing cannot passivate the interface effectively. The breakdown field of gate oxide on the dry etched sample is also degraded. These results indicate that dry etching of SiC surface should be avoided when fabricating MOS devices.

Abstract: Silicon carbide (SiC) is intrinsically more suitable for high temperature operation than silicon. However, for devices and circuits based on metal-oxide-semiconductor, high temperature behavior of gate oxides is still under investigation. This work aims to provide insights on how temperatures from room temperature up to 500 °C affect gate oxide properties of metal-oxide-semiconductor structures. Characterization is performed by current-voltage (I-V) and capacitance-voltage (C-V) measurements with different SiC and polysilicon gate electrode doping types. Increasing breakdown voltages were observed with higher temperatures for n-type SiC doping, while p-type ones break down at lower voltages. Polysilicon doping type only has minor impact on the breakdown voltage but influences the I-V behavior. High temperatures increase the probability of strong inversion being observable in C-V investigation. Regarding the I-V results, it can be stated that the 55 nm gate oxide used in the utilized HT CMOS technology has breakdown voltages above absolute values of around 55 V, independent of any doping types, and no significant current could be observed within the intended 20 V operation range of the technology.

Abstract: Bias temperature instability (BTI) in SiC MOSFETs has come under significant academic and industrial research. Threshold voltage (VTH) shift due to gate voltage stress has been demonstrated in several studies investigating gate oxide reliability in SiC MOSFETs. Results have shown positive.VTH shift occurs due to electron trapping (PBTI), and negative VTH shift occurs due to hole trapping (NBTI). In this paper, VTH shift is studied for unipolar and bipolar gate pulses with frequencies ranging from 1Hz to 100 kHz. The turn-OFF voltage for the unipolar VGS pulse is 0 V. In the case of the bipolar VGS pulses, two turn-OFF voltages are investigated, namely VGS-OFF = -3V and VGS-OFF= -5V. VTH shift is measured after 1000 seconds with recovery times in the range of 20 milliseconds, and preconditioning is performed before VTH measurement. These measurements have been performed at 25°C and 150°C on a commercially available SiC Planar MOSFET and a SiC Trench MOSFET. The results show that -3 V is enough for de-trapping sufficient electrons while -5V results in increased NBTI, which is accelerated by higher temperatures.

Abstract: For the ongoing commercialization of power devices based on 4H-SiC, increasing the yield and improving the reliability of these devices is becoming more and more important. In this investigation, gate oxide on 4H-SiC was examined by time-zero dielectric breakdown (TZDB) and constant current stress (CCS) time-dependent dielectric breakdown (TDDB) method in order to get insights into the influence of the epitaxial defects on the gate oxide performance and reliability. For that purpose, MOS capacitors with different gate oxides have been fabricated. Crystal defects in the epitaxial layers have been detected and mapped by ultraviolet photoluminescence (UVPL) and interference contrast (DIC) imaging. The results of the comparison of electrical data and surface mapping data indicate a negative influence on the leakage current behavior for some extended epitaxial defects. Results from TDDB measurement indicated numerous extrinsic defects, which can be traced back to gate oxide processing conditions and defect densities.

Abstract: In this paper, robustness and reliability differences related to the performance of the gate oxide of commercially-available 1200 V-rated planar and trench SiC MOSFETs have been investigated. Due to a thin gate oxide in SiC MOSFETs and to a naturally imperfect interface of the oxide layer (SiO₂) with the SiC material, its quality and reliability become very important and could be a limiting factor of the SiC technology when compared to the Si one. A dedicated gate oxide step-by-step (V_G SbS) tester has been prepared during which the gate voltage is varied with different profiles. Results of Fowler-Nordheim (FN), Time Dependent Dielectric Breakdown (TDDB) and three test runs of the V_G SbS are presented in this paper. Both technologies show good reliability figures to allow the use in the application. Trench technology shows higher robustness limits whereas the extrapolated reliability at the rated gate voltage is superior for the planar one.

Abstract: In this work, the influence of pre-deposition interfacial oxidation or post-deposition interface nitridation on the performance of 4H-SiC MOS capacitors was investigated. The gate oxide was deposited by LPCVD using TEOS as a precursor. Interface breakdown strength was derived from leakage current and Time-Zero Dielectric Breakdown characteristics whereas interface quality was assessed by the determination of interface state density from the comparison of quasi-static and high frequency capacitance-voltage characteristics using high-low method. In the experimental results, it is demonstrated that the gate oxide deposited by LPCVD using TEOS which is post-deposition annealed in nitric oxide ambient is advantageous for trench-gate MOSFET due to its effectiveness for improving the interface quality and oxide reliability, whereas pre-deposition interfacial oxidation is deleterious to interface state density and breakdown strength.